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Hello Angel Pons, Dinesh Gehlot, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch enables the eSOL config option when libgfx or uGOP is enabled
for early graphics initialization.
BUG=NA
TEST=Able to build google/rex and google/tivviks
Cq-Depend: CB:83769, CB:83770
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/vendorcode/google/chromeos/Kconfig
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/10
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yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83317?usp=email )
Change subject: soc/intel/common/block/gpmr: Allow soc to have specific gpmr definition
......................................................................
Patch Set 8:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83317/comment/335fb5c4_60a1db59?us… :
PS2, Line 7: src/
> Remove "src"
Done
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Change subject: soc/intel/common: Add CPU and PCIe IDs for Snow Ridge platform
......................................................................
Patch Set 8:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/90e09ca1_bd328f10?us… :
PS1, Line 7: add CPU and PCIe definitions for SNR
> Suggestion: […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/85571f0e_f0221c31?us… :
PS3, Line 8:
> These IDs are described in the EDS file of Snow Ridge SoC, I've added it in the commit message.
Done
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/83314/comment/dab2e3a1_eb4b6b58?us… :
PS1, Line 86: #define CPUID_SNOWRIDGE_A0 0x80660
> Yes, I've added it.
Done
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ritul guru has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83757?usp=email )
Change subject: soc/amd/common/psp_smi_flash: add command-specific data structures
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mainboard/intel/frost_creek: Add a new CRB Frost Creek for Snow Ridge
......................................................................
Patch Set 10:
(2 comments)
File src/mainboard/intel/frost_creek/COPYING-NOTICE:
PS3:
> Ok, I've removed it.
Done
File src/mainboard/intel/frost_creek/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/83322/comment/df05fc12_2d671c31?us… :
PS3, Line 22: Store (Arg0, SMIF) // SMI Function
: Store (0,
> Ok, I've updated all asl files to follow ASL2 syntax.
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Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/83767?usp=email )
Change subject: MAINTAINERS: Add Subrata and Pranava for new google/fatcat entry
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83767/comment/5231141b_c173cef3?us… :
PS1, Line 7: Add google/fatcat entry and update maintainers
> Maybe: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83767/comment/e7f7e89f_6ce3f729?us… :
PS1, Line 10: updated
> update
Acknowledged
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