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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
18 files changed, 1,361 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/48
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#50).
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,277 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/50
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83732?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
Details:
- Skeleton files to compile google/fatcat mainboard.
BUG=b:348678529
TEST=Build verified on with using PTL SOC and google/fatcat mainboard.
Change-Id: I4c069ba64f487259ce746dc52296618d91209602
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
6 files changed, 513 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83732/12
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Ronak Kanabar has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )
Change subject: vc/intel/fsp/fsp2_0/ptl: Add placeholder FSP headers to compile
......................................................................
Patch Set 9:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h:
https://review.coreboot.org/c/coreboot/+/83732/comment/8f380c40_0d40025e?us… :
PS9, Line 129: #pragma pack (pop)
> Acknowledged
Once we have generated headers it will have #pragma pack (push, 1) and #pragma pack (pop) same as all the programs. Keep what we have in MTL and other headers.
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Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, V Sowmya, Varun Upadhyay.
Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83781?usp=email )
Change subject: mb/google/trulo: Update ISH GPIO's configuration
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
please submit this CL on top of CB:83656
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