Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80207?usp=email )
Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
nb/intel/*: Match ACPI with resource allocation
Currently resource allocation starts top down from the default value
0xfe000000. This does not match what ACPI reports, so adapt
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT to reflect that.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I2ba0e96a7ab18d65b7fbbb38b1a979ea2ec6d1be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80207
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/i945/Kconfig
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/x4x/Kconfig
7 files changed, 28 insertions(+), 0 deletions(-)
Approvals:
Nico Huber: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 8059e7e..fef0d735 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -31,6 +31,10 @@
int
default 64
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config SMM_RESERVED_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 4b83a25..3540337 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -60,6 +60,10 @@
int
default 64
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default ECAM_MMCONF_BASE_ADDRESS
+
config DCACHE_RAM_BASE
hex
default 0xff7c0000
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index ef925e1..32eff1a 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -41,6 +41,10 @@
int
default 64
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config OVERRIDE_CLOCK_DISABLE
bool
default n
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index ce705dc..2bafebf 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -47,6 +47,10 @@
config ECAM_MMCONF_BUS_NUMBER
default 256
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config INTEL_GMA_BCLV_OFFSET
default 0x48254
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 8778126..59cfcd5 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -38,4 +38,8 @@
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index f7d56c7..fa40b06 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -104,6 +104,10 @@
int
default 64
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default ECAM_MMCONF_BASE_ADDRESS
+
config DCACHE_RAM_BASE
hex
default 0xfefe0000
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 9af0638..097e111 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -28,6 +28,10 @@
int
default 256
+# This number must be equal or lower than what's reported in ACPI PCI _CRS
+config DOMAIN_RESOURCE_32BIT_LIMIT
+ default 0xfec00000
+
config SMM_RESERVED_SIZE
hex
default 0x100000
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Change subject: nb/intel/*: Match ACPI with resource allocation
......................................................................
Patch Set 2: Code-Review+2
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Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83767?usp=email )
Change subject: MAINTAINERS: Add google/fatcat entry and update maintainers
......................................................................
MAINTAINERS: Add google/fatcat entry and update maintainers
Add GOOGLE FATCAT MAINBOARDS section for src/mb/google/fatcat and
updated the maintainers list to add Subrata Banik and Pranava Y N
as maintainers
Change-Id: I5ae0f0d24d43e91c2097c68446bb64b9ae507e2e
Signed-off-by: Pranava Y N <pranavayn(a)google.com>
---
M MAINTAINERS
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/83767/1
diff --git a/MAINTAINERS b/MAINTAINERS
index c960ed6..b94650b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -341,6 +341,11 @@
S: Maintained
F: src/mainboard/google/brya/
+GOOGLE FATCAT MAINBOARDS
+M: Subrata Banik <subratabanik(a)google.com>
+M: Pranava Y N <pranavayn(a)google.com>
+F: src/mainboard/google/fatcat/
+
GOOGLE HATCH MAINBOARDS
M: Subrata Banik <subratabanik(a)google.com>
M: Nick Vaccaro <nvaccaro(a)chromium.org>
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Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email )
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83752/comment/a4c79ef8_5a060637?us… :
PS4, Line 7: Booting
> booting
Done
https://review.coreboot.org/c/coreboot/+/83752/comment/48bf6c75_a54b1eb8?us… :
PS4, Line 9: When battery is disconnected and only adaptor is connected
: higher PL2 power draw causes cpu brown out and system does not
: boot to kernel. To avoid this set Boot frequency UPD to 1.
: Reduce PL4 value to overcome power spikes from SoC during boot.
: Remove Psys implementation since it impacts active state
: platform performance.
> Please reflow for 72 characters per line.
Done
File src/mainboard/google/brox/variants/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/0f93438a_0ec7e1cf?us… :
PS4, Line 19: .pl1_min_power = 15000,
> Please also mention this (and below) in the commit message. […]
Done
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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelley Chen, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83752?usp=email
to look at the new patch set (#5).
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 59 insertions(+), 104 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/5
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Change subject: lib/string: Add strncat() and strcat() functions
......................................................................
Patch Set 2:
(1 comment)
File tests/lib/string-test.c:
https://review.coreboot.org/c/coreboot/+/83765/comment/45bf3cee_c1afb906?us… :
PS2, Line 193: ret = strncat(dst, src, len - 1);
`len` is the size of `str` not `src`. This way the case where the count is smaller than src len is not checked. Same is the case for `test_strcat`
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Change subject: mb/lenovo/t520: Add USB port config into devicetree
......................................................................
Patch Set 2: Code-Review+1
(5 comments)
Patchset:
PS2:
Welcome to coreboot!
Commit Message:
https://review.coreboot.org/c/coreboot/+/83764/comment/943277cd_2812fcbe?us… :
PS2, Line 2: PuFF1k
If possible, it’d be great if you used your full name.
https://review.coreboot.org/c/coreboot/+/83764/comment/0e219b1f_179a9ead?us… :
PS2, Line 11: This change introduces USB port config.
No need to break the line above?
https://review.coreboot.org/c/coreboot/+/83764/comment/44654036_89ae68c3?us… :
PS2, Line 12:
Tested how? Put a USB storage device in each port? Did you do any speed tests?
File src/mainboard/lenovo/t520/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/83764/comment/8ca4b7a3_79cdb304?us… :
PS2, Line 77: }"
One indentation too much?
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Change subject: mb/google/brox: Fix Booting to kernel without battery
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83752/comment/b181bf3d_cf95a9ac?us… :
PS3, Line 9: Set Boot frequency UPD to 1 to avoid higher PL2 power draw when
: only adaptor is connected with battery removed or disconnected.
: Reduce PL4 value to overcome power spikes from SoC during boot.
: Remove Psys implementation since it impacts active state platform
: performance.
> Done
I didn’t see this.
1. Reduce …
2. Remove …
Or, if you do not want to enumerate things, please do not break lines after a sentence ends.
Commit Message:
https://review.coreboot.org/c/coreboot/+/83752/comment/a61124a9_a6f7e6bd?us… :
PS4, Line 7: Booting
booting
https://review.coreboot.org/c/coreboot/+/83752/comment/5303e627_6191e65a?us… :
PS4, Line 9: When battery is disconnected and only adaptor is connected
: higher PL2 power draw causes cpu brown out and system does not
: boot to kernel. To avoid this set Boot frequency UPD to 1.
: Reduce PL4 value to overcome power spikes from SoC during boot.
: Remove Psys implementation since it impacts active state
: platform performance.
Please reflow for 72 characters per line.
File src/mainboard/google/brox/variants/brox/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/5e5e3753_336e95dc?us… :
PS4, Line 19: .pl1_min_power = 15000,
Please also mention this (and below) in the commit message. Or did I miss it?
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