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Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL defines
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/83773/comment/1f0f2c7c_af5305ce?us… :
PS1, Line 80: /* Re-purpose unused SPI controller register bit for semaphore to synchronize
: SPI access between SMM and non-SMM software/OS driver. */
: #define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4)
> any reason to add this now, rather than in the patch in which it's used? seems unrelated to the MISC […]
no real reason tbh. moving that to CB:83775 would make sense
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#52).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,272 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/52
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Change subject: soc/amd/common/psp_smi_flash: add command-specific data structures
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/psp_smi: implement P2C mailbox handling
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Since this is a software feature and not actually about the PSP, shouldn't this go someplace other t […]
it's software that talks to the other psp mailbox, so i'd say that it should be in amd/common/block/psp
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Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL defines
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/83773/comment/0a19019c_418d4417?us… :
PS1, Line 80: /* Re-purpose unused SPI controller register bit for semaphore to synchronize
: SPI access between SMM and non-SMM software/OS driver. */
: #define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4)
any reason to add this now, rather than in the patch in which it's used? seems unrelated to the MISC_CTRL
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Change subject: soc/amd/common/psp: add and call PSP SMI SPI access function stubs
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/common/psp_smi: implement P2C mailbox handling
......................................................................
Patch Set 4:
(3 comments)
Patchset:
PS4:
Since this is a software feature and not actually about the PSP, shouldn't this go someplace other than amd/common/block/psp?
File src/soc/amd/common/block/psp/psp_smi.c:
https://review.coreboot.org/c/coreboot/+/83740/comment/67dd40a3_5b773cfe?us… :
PS4, Line 33: tmp
Nit: I know that the union is already named status, but why tmp and not something like 'status'? I mean, all variables are temporary.
Same below.
https://review.coreboot.org/c/coreboot/+/83740/comment/c4c3b3de_62b5e3d3?us… :
PS4, Line 80: u32
Nit: this seems to use a mix of u8/u32 and uint8_t/uint32_t. Can we standardize on one?
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Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL defines
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/83773/comment/b9a10fec_1c23b5ce?us… :
PS1, Line 80: Re-purpose unused
Maybe: "AMD has re-purposed this"
That way it doesn't seem like something just being done here in coreboot.
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