Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82555?usp=email )
Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
......................................................................
mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
Depending on how firmware image was passed to QEMU, it may behave as:
- ROM - memory mapped reads, writes are ignored (FW image mounted with
'-bios');
- RAM - memory mapped reads and writes (FW image mounted with e.g.
'-device loader');
- flash - memory mapped reads, write and erase possible through
commands. Contrary to physical flash devices erase is not required
before writing, but it also doesn't hurt. Flash may be split into
read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd.
Combined size of system firmware must not exceed 8 MiB by default
(FW image(s) mounted with '-drive if=pflash').
This function detects which of the above applies and fills
region_device_ops accordingly.
Tested by starting QEMU with firmware passed as '-drive if=pflash',
'-drive if=pflash,readonly=on' and '-bios'. When started with firmware
passed through '-device loader', coreboot complains about corrupted
FMAP, but this is the same behavior as without this change:
[ERROR] Invalid FMAP at 0x40000
[EMERG] Cannot locate primary CBFS
Writable pflash support was added about 17 years ago, so it should be
supported by all QEMU versions currently in use. Since QEMU 5.0.0 it is
possible to change the limit of firmware size with `max-fw-size` machine
configuration option, up to 16 MiB, as bigger sizes would overlap with
default IO APIC memory range.
Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82555
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-i440fx/Makefile.mk
A src/mainboard/emulation/qemu-i440fx/rom_media.c
M src/mainboard/emulation/qemu-q35/Kconfig
M src/mainboard/emulation/qemu-q35/Makefile.mk
5 files changed, 217 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
Sergii Dmytruk: Looks good to me, approved
diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig
index 24dfa7a2..842c053 100644
--- a/src/mainboard/emulation/qemu-i440fx/Kconfig
+++ b/src/mainboard/emulation/qemu-i440fx/Kconfig
@@ -19,6 +19,7 @@
select NO_SMM
select BOOT_DEVICE_NOT_SPI_FLASH
select BOOT_DEVICE_MEMORY_MAPPED
+ select BOOT_DEVICE_SUPPORTS_WRITES
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.mk b/src/mainboard/emulation/qemu-i440fx/Makefile.mk
index 7d6041b..6ff2f73 100644
--- a/src/mainboard/emulation/qemu-i440fx/Makefile.mk
+++ b/src/mainboard/emulation/qemu-i440fx/Makefile.mk
@@ -7,6 +7,7 @@
ramstage-y += memmap.c
ramstage-y += northbridge.c
+ramstage-y += rom_media.c
all-y += fw_cfg.c
all-y += bootmode.c
diff --git a/src/mainboard/emulation/qemu-i440fx/rom_media.c b/src/mainboard/emulation/qemu-i440fx/rom_media.c
new file mode 100644
index 0000000..d2469ba
--- /dev/null
+++ b/src/mainboard/emulation/qemu-i440fx/rom_media.c
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Inspired by OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c from edk2 */
+
+#include <arch/mmio.h>
+#include <boot_device.h>
+#include <console/console.h>
+#include <commonlib/helpers.h>
+#include <commonlib/region.h>
+#include <string.h>
+
+#define WRITE_BYTE_CMD 0x10
+#define BLOCK_ERASE_CMD 0x20
+#define CLEAR_STATUS_CMD 0x50
+#define READ_STATUS_CMD 0x70
+#define BLOCK_ERASE_CONFIRM_CMD 0xD0
+#define READ_ARRAY_CMD 0xFF
+
+#define CLEARED_ARRAY_STATUS 0x00
+
+#define QEMU_FLASH_BLOCK_SIZE 0x1000
+
+#if CONFIG(ELOG)
+#include <southbridge/intel/common/pmutil.h>
+
+/*
+ * ELOG and VBOOT options are automatically enabled when building with
+ * CHROMEOS=y. While the former allows for logging PCH state (not that there is
+ * much to log on QEMU), the latter currently forces 16 MiB ROM size, which in
+ * turn doesn't allow mounting as pflash in QEMU. Using pflash is required to
+ * have writable flash, which means that the following function will not be
+ * able to write to the flash based log until ROM size and layout is changed in
+ * Flashmap used when building for vboot.
+ */
+void pch_log_state(void) {}
+#endif
+
+static ssize_t qemu_writeat(const struct region_device *rd, const void *b,
+ size_t offset, size_t size)
+{
+ const struct mem_region_device *mdev;
+ size_t i;
+ volatile char *ptr;
+ const char *buf = b;
+
+ mdev = container_of(rd, __typeof__(*mdev), rdev);
+ ptr = &mdev->base[offset];
+
+ for (i = 0; i < size; i++) {
+ write8(ptr, WRITE_BYTE_CMD);
+ write8(ptr, buf[i]);
+ ptr++;
+ }
+
+ /* Restore flash to read mode. */
+ if (size > 0) {
+ write8(ptr - 1, READ_ARRAY_CMD);
+ }
+
+ return size;
+}
+
+static ssize_t qemu_eraseat(const struct region_device *rd, size_t offset,
+ size_t size)
+{
+ const struct mem_region_device *mdev;
+ size_t i;
+ volatile char *ptr;
+
+ mdev = container_of(rd, __typeof__(*mdev), rdev);
+ ptr = &mdev->base[offset];
+
+ if (!IS_ALIGNED(offset, QEMU_FLASH_BLOCK_SIZE)) {
+ printk(BIOS_ERR, "%s: erased offset isn't multiple of block size\n",
+ __func__);
+ return -1;
+ }
+
+ if (!IS_ALIGNED(size, QEMU_FLASH_BLOCK_SIZE)) {
+ printk(BIOS_ERR, "%s: erased size isn't multiple of block size\n",
+ __func__);
+ return -1;
+ }
+
+ for (i = 0; i < size; i += QEMU_FLASH_BLOCK_SIZE) {
+ write8(ptr, BLOCK_ERASE_CMD);
+ write8(ptr, BLOCK_ERASE_CONFIRM_CMD);
+ ptr += QEMU_FLASH_BLOCK_SIZE;
+ }
+
+ /* Restore flash to read mode. */
+ if (size > 0) {
+ write8(ptr - QEMU_FLASH_BLOCK_SIZE, READ_ARRAY_CMD);
+ }
+
+ return size;
+}
+
+static struct region_device_ops flash_ops;
+static struct mem_region_device boot_dev;
+
+/*
+ * Depending on how firmware image was passed to QEMU, it may behave as:
+ *
+ * - ROM - memory mapped reads, writes are ignored (FW image mounted with
+ * '-bios');
+ * - RAM - memory mapped reads and writes (FW image mounted with e.g.
+ * '-device loader');
+ * - flash - memory mapped reads, write and erase possible through commands.
+ * Contrary to physical flash devices erase is not required before writing,
+ * but it also doesn't hurt. Flash may be split into read-only and read-write
+ * parts, like OVMF_CODE.fd and OVMF_VARS.fd. Maximal combined size of system
+ * firmware is hardcoded (QEMU < 5.0.0) or set by default to 8 MiB. On QEMU
+ * version 5.0.0 or newer, it is configurable with `max-fw-size` machine
+ * configuration option, up to 16 MiB to not overlap with IOAPIC memory range
+ * (FW image(s) mounted with '-drive if=pflash').
+ *
+ * This function detects which of the above applies and fills region_device_ops
+ * accordingly.
+ */
+void boot_device_init(void)
+{
+ volatile char *ptr;
+ char original, readback;
+ static bool initialized = false;
+
+ if (initialized)
+ return;
+
+ /*
+ * mmap, munmap and readat are always identical to mem_rdev_rw_ops, other
+ * functions may vary.
+ */
+ flash_ops = mem_rdev_rw_ops;
+
+ boot_dev.base = (void *)(uintptr_t)(0x100000000ULL - CONFIG_ROM_SIZE);
+ boot_dev.rdev.ops = &flash_ops;
+ boot_dev.rdev.region.size = CONFIG_ROM_SIZE;
+
+ /*
+ * Find first byte different than any of the commands, simplified.
+ *
+ * Detection code few lines below writes commands and tries to read back
+ * the response. To make that code simpler, make sure that original byte
+ * is different than any of the commands or expected responses. It is
+ * expected that such byte will always be found - it is virtually
+ * impossible to write valid x86 code with just bytes ending with 0, and
+ * there are also ASCII characters in metadata (CBFS, FMAP) that has bytes
+ * matching those assumptions.
+ */
+ ptr = (volatile char *)boot_dev.base;
+ original = read8(ptr);
+ while (original == (char)0xFF || (original & 0x0F) == 0)
+ original = read8(++ptr);
+
+ /*
+ * Detect what type of flash we're dealing with. This also clears any stale
+ * status bits, so the next read of status register should return known
+ * value (if pflash is used).
+ */
+ write8(ptr, CLEAR_STATUS_CMD);
+ readback = read8(ptr);
+ if (readback == CLEAR_STATUS_CMD) {
+ printk(BIOS_DEBUG, "QEMU flash behaves as RAM\n");
+ /* Restore original content. */
+ write8(ptr, original);
+ } else {
+ /* Either ROM or QEMU flash implementation. */
+ write8(ptr, READ_STATUS_CMD);
+ readback = read8(ptr);
+ if (readback == original) {
+ printk(BIOS_DEBUG, "QEMU flash behaves as ROM\n");
+ /* ROM means no writing nor erasing. */
+ flash_ops.writeat = NULL;
+ flash_ops.eraseat = NULL;
+ } else if (readback == CLEARED_ARRAY_STATUS) {
+ /* Try writing original value to test whether flash is writable. */
+ write8(ptr, WRITE_BYTE_CMD);
+ write8(ptr, original);
+ write8(ptr, READ_STATUS_CMD);
+ readback = read8(ptr);
+ if (readback & 0x10 /* programming error */) {
+ printk(BIOS_DEBUG,
+ "QEMU flash behaves as write-protected flash\n");
+ flash_ops.writeat = NULL;
+ flash_ops.eraseat = NULL;
+ } else {
+ printk(BIOS_DEBUG, "QEMU flash behaves as writable flash\n");
+ flash_ops.writeat = qemu_writeat;
+ flash_ops.eraseat = qemu_eraseat;
+ }
+ /* Restore flash to read mode. */
+ write8(ptr, READ_ARRAY_CMD);
+ } else {
+ printk(BIOS_ERR, "Unexpected QEMU flash behavior, assuming ROM\n");
+ /*
+ * This shouldn't happen and first byte of flash may already be
+ * corrupted by testing, but don't take any further risk.
+ */
+ flash_ops.writeat = NULL;
+ flash_ops.eraseat = NULL;
+ }
+ }
+
+ initialized = true;
+}
+
+/* boot_device_ro() is defined in arch/x86/mmap_boot.c */
+const struct region_device *boot_device_rw(void)
+{
+ return &boot_dev.rdev;
+}
diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 11ea750..2fb180b 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -17,6 +17,7 @@
select MAINBOARD_HAS_CHROMEOS
select BOOT_DEVICE_NOT_SPI_FLASH
select BOOT_DEVICE_MEMORY_MAPPED
+ select BOOT_DEVICE_SUPPORTS_WRITES
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.mk b/src/mainboard/emulation/qemu-q35/Makefile.mk
index bc73edc..a60fbd6 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.mk
+++ b/src/mainboard/emulation/qemu-q35/Makefile.mk
@@ -12,6 +12,7 @@
ramstage-y += ../qemu-i440fx/memmap.c
ramstage-y += ../qemu-i440fx/northbridge.c
+ramstage-y += ../qemu-i440fx/rom_media.c
ramstage-y += memmap.c
ramstage-y += cpu.c
@@ -20,4 +21,5 @@
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-y += ../qemu-i440fx/rom_media.c
smm-y += memmap.c
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Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83778?usp=email )
Change subject: soc/amd/common/psp_smi_flash: add buffer overflow checks
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/psp/psp_smi_flash.c:
https://review.coreboot.org/c/coreboot/+/83778/comment/5789247e_81462dc3?us… :
PS1, Line 251: if (!is_valid_rw_byte_count(cmd_buf, num_bytes))
: return MBOX_PSP_COMMAND_PROCESS_ERROR;
> adding a warning sounds good to me; will do
Done
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Change subject: soc/amd/common/psp_smi_flash: implement SPI read/write/erase command
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83777/comment/e4672346_34adeb71?us… :
PS1, Line 7: wrire
> write
Done
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Change subject: soc/amd/common/psp_smi_flash: implement SPI read/write/erase command
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/psp/psp_smi_flash.c:
https://review.coreboot.org/c/coreboot/+/83777/comment/ad667639_9a14d7e5?us… :
PS1, Line 237: }
> this code is in smm, so when that code gets interrupted, we have much larger issues, since the smm c […]
updated the commit message of the previous patch since that's the one that first uses spi_controller_available
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Change subject: soc/amd/common/psp_smi_flash: implement SPI read/write/erase command
......................................................................
soc/amd/common/psp_smi_flash: implement SPI read/write/erase command
Use coreboot's SPI flash access infrastructure to do the flash read,
write, or erase operations as requested from the PSP.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I4957a6d316015cc7037acf52facb6cc69188d446
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
1 file changed, 112 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83777/3
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Hello Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier, build bot (Jenkins), ritul guru,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/amd/common/psp_smi_flash: implement SPI info command
......................................................................
soc/amd/common/psp_smi_flash: implement SPI info command
Detect the block size of the SPI flash and number of flash blocks
reserved for the flash region corresponding to the 'target_nv_id' field
in the command buffer. This information is then written to the
corresponding fields in the command buffer. Since detecting the flash
chip still might result in accesses to it, make sure that it's available
for use and not currently used by an OS driver. Since this code is
inside the SMI handler, we don't have to worry about this code to be
interrupted, so we don't need to set some bit to tell other code that
we're currently using the SPI controller in the SMI handler.
This patch is a modified version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
---
M src/soc/amd/common/block/psp/psp_smi_flash.c
1 file changed, 43 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/83776/3
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Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I19041a27a9e8f901d42c3f60af834df625455ea6
Gerrit-Change-Number: 83776
Gerrit-PatchSet: 3
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com>
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