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Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define
......................................................................
Patch Set 1:
(2 comments)
File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/83773/comment/78261e66_488725a4?us… :
PS1, Line 80: Re-purpose unused
> Maybe: "AMD has re-purposed this" […]
Done in CB:83775
https://review.coreboot.org/c/coreboot/+/83773/comment/3aafd1ef_e6a74094?us… :
PS1, Line 80: /* Re-purpose unused SPI controller register bit for semaphore to synchronize
: SPI access between SMM and non-SMM software/OS driver. */
: #define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4)
> no real reason tbh. […]
Done
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Change subject: soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define
......................................................................
soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define
This register is currently used by the SPI DMA code that sets an
undocumented bit. A later patch will add and use some other bit in this
register.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/lpc/spi_dma.c
2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83773/2
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Change subject: soc/amd/common/psp_smi_flash: add spi_controller_available
......................................................................
soc/amd/common/psp_smi_flash: add spi_controller_available
The SPI_SEMAPHORE_DRIVER_LOCKED bit in the SPI_MISC_CNTRL register
doesn't affect the hardware, but it re-used by AMD as a semaphore to
synchronize the access to the SPI controller between SMM and non-SMM
software like an OS-level driver. Since it doesn't affect the hardware,
it's marked as reserved in the PPRs. Add the 'spi_controller_available'
helper function to check this bit to see if some software or driver
outside of SMM is currently using the SPI flash controller to avoid
interfering with that operation.
This patch is a slightly reworked version of parts of CB:65523.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I49218e03a5dd555b2b2d34eaad86673e9fc908c3
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/psp/psp_smi_flash.c
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/83775/2
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Change subject: soc/amd/common/psp_smi: implement P2C mailbox handling
......................................................................
soc/amd/common/psp_smi: implement P2C mailbox handling
When the PSP wants to access the SPI flash during runtime, but isn't the
owner of the SPI flash controller, it sends an SMI to the x86 side. The
corresponding SMI handler then checks the P2C (PSP to core) mailbox for
the command and data, processes the command, and if needed puts the
requested data into the P2C buffer.
The P2C mailbox is a memory region in TSEG aka SMM memory. Both location
and size are communicated to the PSP via the PSP SMM info mailbox
command which is sent right after mpinit is done.
This commit adds the code to access the P2C mailbox to the PSP SMI
handler code, but the handling of the actual mailbox commands the PSP
sends to the SMI handler is added in later patches to keep the patch
size manageable.
This patch is a heavily reworked version of parts of CB:65523.
Document #55758 Rev. 2.04 was used as a reference.
Test=When selecting SOC_AMD_COMMON_BLOCK_PSP_SMI, Mandolin still builds
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com>
Change-Id: I50479bed2332addae652026c6818460eeb6403af
---
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_smi.c
M src/soc/amd/common/block/psp/psp_smm.c
3 files changed, 174 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83740/5
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Change subject: soc/amd/common/psp_smi_flash: implement SPI read/wrire/erase command
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83777/comment/1eef9251_80ff82a3?us… :
PS1, Line 7: wrire
write
File src/soc/amd/common/block/psp/psp_smi_flash.c:
https://review.coreboot.org/c/coreboot/+/83777/comment/f229e7da_4a11a976?us… :
PS1, Line 237: }
do we need to mark the spi controller as busy when we're using it? If not, what keeps something else from using it?
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Change subject: soc/amd/common/psp_smi_flash: implement SPI info command
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,272 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/53
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Change subject: soc/amd/common/psp_smi_flash: add spi_controller_available
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/common/psp_smi_flash: add find_psp_spi_flash_device_region
......................................................................
Patch Set 1: Code-Review+2
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Martin Roth has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/83758?usp=email )
Change subject: soc/amd/common/psp_smi_flash: validate target SPI region ID
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Patch Set 3: Code-Review+2
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