coreboot-gerrit August 2024

coreboot-gerrit@coreboot.org

1 participants
3913 discussions

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Subrata Banik (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Ravishankar Sarawadi, Saurabh Mishra, Tarun. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 51: (14 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83354/comment/122cedc9_c9e6eb69?us… : PS51, Line 43: GFx GFX ? File src/soc/intel/pantherlake/bootblock/pcd.c: https://review.coreboot.org/c/coreboot/+/83354/comment/240b62b4_97a26e78?us… : PS51, Line 17: #include <soc/bootblock.h> please follow order https://review.coreboot.org/c/coreboot/+/83354/comment/fb3d3e9c_42cc3ff6?us… : PS51, Line 26: #define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xA80 : #define PCR_PSFX_TO_SHDW_BAR0 0 : #define PCR_PSFX_TO_SHDW_BAR1 0x4 : #define PCR_PSFX_TO_SHDW_BAR2 0x8 : #define PCR_PSFX_TO_SHDW_BAR3 0xC : #define PCR_PSFX_TO_SHDW_BAR4 0x10 : #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 : #define PCR_PSFX_T0_SHDW_PCIEN 0x1C ```suggestion #define PCR_PSF8_TO_SHDW_PMC_REG_BASE 0xA80 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 #define PCR_PSFX_TO_SHDW_BAR3 0xC #define PCR_PSFX_TO_SHDW_BAR4 0x10 #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C ``` https://review.coreboot.org/c/coreboot/+/83354/comment/0927f00b_d1fe67fd?us… : PS51, Line 35: #define PCR_DMI_ACPIBA 0x27B4 : #define PCR_DMI_ACPIBDID 0x27B8 : #define PCR_DMI_PMBASEA 0x27AC : #define PCR_DMI_PMBASEC 0x27B0 remove these macros, not in use https://review.coreboot.org/c/coreboot/+/83354/comment/ca280315_1c5020df?us… : PS51, Line 130: /* PCR_PSF8_TO_SHDW_PMC_REG_BASE is not proper or needs reprogramming */ why we need this ? https://review.coreboot.org/c/coreboot/+/83354/comment/5fa22c76_e5233525?us… : PS51, Line 131: printk(BIOS_WARNING, "PMC PCR_PSF8 not properly aligned: pmc_reg_value=%x\n", pmc_reg_value); ```suggestion printk(BIOS_WARNING, "PCR_PSFX_TO_SHDW_BAR4 has not been programmed. \n"); ``` File src/soc/intel/pantherlake/bootblock/report_platform.c: https://review.coreboot.org/c/coreboot/+/83354/comment/a6fae239_f18163ab?us… : PS51, Line 109: GT2_1 ```suggestion { PCI_DID_INTEL_PTL_U_GT2_1, "Pantherlake-U GT2" }, ``` https://review.coreboot.org/c/coreboot/+/83354/comment/9fba6331_e77f5d0c?us… : PS51, Line 110: GT2_1 same as above File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/83354/comment/fca66e0d_a8dad49d?us… : PS51, Line 19: #define SAF_BASE_ADDRESS 0x3ffe000000 : #define SAF_BASE_SIZE 0x2000000 I thought you told me this address has now moved within < 4GB range but you have still kept a > 4GB value. is that to address my review comment ? File src/soc/intel/pantherlake/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/83354/comment/23cf7b63_475e6848?us… : PS51, Line 14: #define PID_PSF15 0xB4 : #define PID_PSF14 0xB3 : #define PID_PSF8 0xB2 : #define PID_PSF6 0xB1 : #define PID_PSF4 0xB0 : #define PID_PSF0 0xB5 : #define PID_CSME0 0x40 : #define PID_PSTH 0x6A : #define PID_ITSS 0x69 : #define PID_RTC 0x6C : #define PID_ISCLK 0x72 : #define PID_IOM 0x80 : #define PID_DMI 0x2F : #define PID_NPK 0x8C : #define PID_XHCI 0x3A ```suggestion #define PID_DMI 0x2F #define PID_XHCI 0x3A #define PID_CSME0 0x40 #define PID_GPIOCOM0 0x59 #define PID_GPIOCOM1 0x5A #define PID_GPIOCOM3 0x5B #define PID_GPIOCOM4 0x5C #define PID_GPIOCOM5 0x5D #define PID_ITSS 0x69 #define PID_PSTH 0x6A #define PID_RTC 0x6C #define PID_ISCLK 0x72 #define PID_IOM 0x80 #define PID_NPK 0x8C #define PID_PSF4 0xB0 #define PID_PSF6 0xB1 #define PID_PSF8 0xB2 #define PID_PSF14 0xB3 #define PID_PSF15 0xB4 #define PID_PSF0 0xB5 ``` File src/soc/intel/pantherlake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/83354/comment/d590bb97_80c15d52?us… : PS51, Line 76: #define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ : #define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ : #define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ : #define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ : #define GPE_STS_RSVD GPE_STD : #define WADT_STS BIT(18) : #define GPIO_T2_STS BIT(15) : #define ESPI_STS BIT(14) : #define PME_B0_STS BIT(13) : #define ME_SCI_STS BIT(12) : #define PME_STS BIT(11) : #define BATLOW_STS BIT(10) : #define PCI_EXP_STS BIT(9) : #define SMB_WAK_STS BIT(7) : #define TCOSCI_STS BIT(6) : #define SWGPE_STS BIT(2) : #define HOT_PLUG_STS BIT(1) ```suggestion #define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ #define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ #define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ #define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ #define GPE_STS_RSVD GPE_STD #define WADT_STS BIT(18) #define GPIO_T2_STS BIT(15) #define ESPI_STS BIT(14) #define PME_B0_STS BIT(13) #define ME_SCI_STS BIT(12) #define PME_STS BIT(11) #define BATLOW_STS BIT(10) #define PCI_EXP_STS BIT(9) #define SMB_WAK_STS BIT(7) #define TCOSCI_STS BIT(6) #define SWGPE_STS BIT(2) #define HOT_PLUG_STS BIT(1) ``` https://review.coreboot.org/c/coreboot/+/83354/comment/385b86cb_15273a04?us… : PS51, Line 94: #define WADT_EN BIT(18) : #define GPIO_T2_EN BIT(15) : #define ESPI_EN BIT(14) : #define PME_B0_EN_BIT 13 : #define PME_B0_EN BIT(PME_B0_EN_BIT) : #define ME_SCI_EN BIT(12) : #define PME_EN BIT(11) : #define BATLOW_EN BIT(10) : #define PCI_EXP_EN BIT(9) : #define TCOSCI_EN BIT(6) : #define SWGPE_EN BIT(2) : #define HOT_PLUG_EN BIT(1) ```suggestion #define WADT_EN BIT(18) #define GPIO_T2_EN BIT(15) #define ESPI_EN BIT(14) #define PME_B0_EN_BIT 13 #define PME_B0_EN BIT(PME_B0_EN_BIT) #define ME_SCI_EN BIT(12) #define PME_EN BIT(11) #define BATLOW_EN BIT(10) #define PCI_EXP_EN BIT(9) #define TCOSCI_EN BIT(6) #define SWGPE_EN BIT(2) #define HOT_PLUG_EN BIT(1) ``` https://review.coreboot.org/c/coreboot/+/83354/comment/bcd73280_0bde859e?us… : PS51, Line 106: : #define EN_BLOCK 3 there is no user i assume File src/soc/intel/pantherlake/soc_info.c: https://review.coreboot.org/c/coreboot/+/83354/comment/6a9e0864_1f276911?us… : PS51, Line 26: CONFIG_MAX_TBT_ROOT_PORTS If you have added this Kconfig as part of this CL, then the default value should also be present in the same CL, correct? the same logic applies to others as well -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 51 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 06 Aug 2024 15:22:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: acpi/acpigen_ps2_keybd: Fix total keymap size calculation
by Felix Held (Code Review) 06 Aug '24

06 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83694?usp=email ) Change subject: acpi/acpigen_ps2_keybd: Fix total keymap size calculation ...................................................................... acpi/acpigen_ps2_keybd: Fix total keymap size calculation This patch move keymap size calculation inside of has_alpha_num_punct_keys condition. When the condition is not met, it can prevent total keymaps size calculate incorrectly. BUG=none TEST=emerge coreboot pass Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83694 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/acpi/acpigen_ps2_keybd.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 8691207..75e0b73 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -287,9 +287,10 @@ keymap = rest_of_keymaps[i]; acpi_dp_add_integer(dp_array, NULL, keymap); } + + total += ARRAY_SIZE(rest_of_keymaps); } - total += ARRAY_SIZE(rest_of_keymaps); printk(BIOS_INFO, "PS2K: Passing %u keymaps to kernel\n", total); acpi_dp_add_array(dp, dp_array); -- To view, visit https://review.coreboot.org/c/coreboot/+/83694?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dcf31d89924c1a8f2768e42065761b361e9ca41 Gerrit-Change-Number: 83694 Gerrit-PatchSet: 11 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[M] Change in coreboot[main]: mb/google/brox/var/jubilant: Update WWAN and UsbCam Settings
by Felix Held (Code Review) 06 Aug '24

06 Aug '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83766?usp=email ) Change subject: mb/google/brox/var/jubilant: Update WWAN and UsbCam Settings ...................................................................... mb/google/brox/var/jubilant: Update WWAN and UsbCam Settings Update GPIOs for WWAN and USB Camera functions. BUG=b:341188351 TEST=Build and verify on jubilant Change-Id: I145aa994767ddc59be519b96017af71badf82734 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83766 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/gpio.c M src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h 2 files changed, 47 insertions(+), 5 deletions(-) Approvals: David Wu: Looks good to me, approved Ren Kuo: Looks good to me, but someone else must approve Sheng-Liang Pan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c index a6f1b5b..0b7ea77 100644 --- a/src/mainboard/google/brox/variants/jubilant/gpio.c +++ b/src/mainboard/google/brox/variants/jubilant/gpio.c @@ -8,7 +8,29 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { - + /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> WWAN_CFG0 */ + PAD_CFG_GPI(GPP_E11, NONE, PLTRST), + /* GPP_E17 : [NF2: THC0_SPI1_INT# NF6: USB_C_GPP_E17] ==> WWAN_CFG02 */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* GPP_D7 : SRCCLKREQ2_L ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_D7, 1, DEEP), + /* GPP_D5 : SRCCLKREQ0_L ==> WWAN_SAR_ODL */ + PAD_CFG_GPO(GPP_D5, 1, DEEP), + /* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> WWAN_WLAN_COEX1 */ + PAD_CFG_GPI(GPP_S4, NONE, DEEP), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> WWAN_WLAN_COEX2 */ + PAD_CFG_GPI(GPP_S5, NONE, DEEP), + /* GPP_F6 : [NF1: CNV_PA_BLANKING NF6: USB_C_GPP_F6] ==>WWAN_WLAN_COEX3 */ + PAD_CFG_GPI(GPP_F6, NONE, DEEP), + /* + * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] + * ==> WWAN_PWR_EN + */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_H23, 1, LOCK_CONFIG), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> EN_FP_PWR (active high) */ PAD_CFG_GPO_LOCK(GPP_D2, 0, LOCK_CONFIG), @@ -32,6 +54,9 @@ /* GPP_F14 : [NF1: GSXDIN NF3: THC1_SPI2_IO2 NF6: USB_C_GPP_F14] ==> PCH_TCHSCR_REPORT_EN */ PAD_CFG_GPO(GPP_F14, 0, DEEP), + /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> EN_UCAM_PWR */ + PAD_CFG_GPO(GPP_E7, 1, PLTRST), + /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> PCH_I2C_MISC_R_SDA (SAR, HP) */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), /* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> PCH_I2C_MISC_R_SCL (SAR, HP) */ @@ -84,6 +109,15 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + + /* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), + /* + * GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] + * ==> WWAN_PWR_EN + */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. * To ensure proper power sequencing for the FPMCU device, reset signal is driven low @@ -95,22 +129,26 @@ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), - /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_F9, 0, DEEP), /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_S7, NONE, DEEP), @@ -142,6 +180,7 @@ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 0, DEEP), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ PAD_CFG_GPI(GPP_E15, NONE, PLTRST), /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ @@ -152,12 +191,14 @@ PAD_CFG_GPI(GPP_E10, NONE, PLTRST), /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_CH_SEL */ PAD_CFG_GPI(GPP_S7, NONE, DEEP), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ PAD_CFG_GPO(GPP_F7, 1, PLTRST), - /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_F9, 1, DEEP), /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ PAD_CFG_GPO(GPP_F17, 0, DEEP), + + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h b/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h index ebc8dee..1d660cf 100644 --- a/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h +++ b/src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h @@ -8,5 +8,6 @@ #define T1_OFF_MS 16 #define T2_OFF_MS 2 #define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_H23 #endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I145aa994767ddc59be519b96017af71badf82734 Gerrit-Change-Number: 83766 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 06 Aug '24

06 Aug '24

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Ravishankar Sarawadi, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83354?usp=email to look at the new patch set (#51). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Includes additional minimal code required to compile the PTL SoC and google/fatcat mainbaord. 5. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/bootblock/bootblock.c A src/soc/intel/pantherlake/bootblock/pcd.c A src/soc/intel/pantherlake/bootblock/report_platform.c A src/soc/intel/pantherlake/espi.c A src/soc/intel/pantherlake/include/soc/bootblock.h A src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pci_devs.h A src/soc/intel/pantherlake/include/soc/pcr_ids.h A src/soc/intel/pantherlake/include/soc/pm.h A src/soc/intel/pantherlake/include/soc/smbus.h A src/soc/intel/pantherlake/include/soc/soc_info.h A src/soc/intel/pantherlake/soc_info.c 15 files changed, 1,277 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/51 -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 51 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

1 0

[S] Change in coreboot[main]: arch/riscv/pmp: Add print macro
by Maximilian Brune (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Arthur Heymans, Philipp Hug, Ron Minnich. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83056?usp=email ) Change subject: arch/riscv/pmp: Add print macro ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83056/comment/9960e47c_f5eb6d76?us… : PS2, Line 9: This adds a printk macro in the PMP code to avoid all harts writing onto : the serial which causes crappy/broken output. : > What is the problem exactly? Are spinlocks broken? The problem is that currently all harts/cores are printing that information on the console. But we only need it to be printed by one of them (at least in my opinion since all harts/cores are configured the same). So instead of synchronizing it and let it be printed by all of them I chose to only let it be printed by the working hart (aka BSP). -- To view, visit https://review.coreboot.org/c/coreboot/+/83056?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaded168bd7302ad1ea29bebb7900810ebeff92d Gerrit-Change-Number: 83056 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 06 Aug 2024 12:26:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/trulo: Update ISH GPIO's configuration
by Varun Upadhyay (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj. Varun Upadhyay has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83781?usp=email ) Change subject: mb/google/brya/var/trulo: Update ISH GPIO's configuration ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83781/comment/627a58f7_651bcf0e?us… : PS2, Line 7: mb/google/trulo > mb/google/brya/var/trulo updated commit msg -- To view, visit https://review.coreboot.org/c/coreboot/+/83781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Gerrit-Change-Number: 83781 Gerrit-PatchSet: 3 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Aug 2024 12:19:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/trulo: Update ISH GPIO's configuration
by Varun Upadhyay (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Varun Upadhyay. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83781?usp=email to look at the new patch set (#3). Change subject: mb/google/brya/var/trulo: Update ISH GPIO's configuration ...................................................................... mb/google/brya/var/trulo: Update ISH GPIO's configuration This patch configures the GPIO pins to enable ISH on the Trulo device, in accordance with schematic_20240607. BUG=b:354607924 TEST=Builds successfully for google/trulo. Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/83781/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Gerrit-Change-Number: 83781 Gerrit-PatchSet: 3 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[S] Change in coreboot[main]: mb/google/trulo: Update ISH GPIO's configuration
by V Sowmya (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Varun Upadhyay. V Sowmya has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83781?usp=email ) Change subject: mb/google/trulo: Update ISH GPIO's configuration ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3af478762e0a0aa35a2698e0ed87a4d8c24362f0 Gerrit-Change-Number: 83781 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Aug 2024 12:10:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mb/google/trulo/var/orisa: Update ISH GPIO's configuration
by V Sowmya (Code Review) 06 Aug '24

06 Aug '24

Attention is currently required from: Deepti Deshatty, Dinesh Gehlot, Eric Lai, Kapil Porwal, Li Feng, Li1 Feng, Nick Vaccaro, Rishika Raj, Varun Upadhyay. V Sowmya has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/83656?usp=email ) Change subject: mb/google/trulo/var/orisa: Update ISH GPIO's configuration ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I24745ba629c59c092ce676b29915e356a4d8d8af Gerrit-Change-Number: 83656 Gerrit-PatchSet: 5 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Li Feng <li1.feng(a)intel.corp-partner.google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Tue, 06 Aug 2024 12:10:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2024