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Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83635?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 73:
(6 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/172cc4b0_76eb00d2?us… :
PS64, Line 108: 12
> this is correct for PTL-UH […]
Sure, added the PCH details.
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/cd5f40f6_b28d9493?us… :
PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */
: enum lpm_state_mask {
: LPM_S0i2_0 = BIT(0),
: LPM_S0i2_1 = BIT(1),
: LPM_S0i2_2 = BIT(2),
: LPM_S0i3_0 = BIT(3),
: LPM_S0i3_1 = BIT(4),
: LPM_S0i3_2 = BIT(5),
: LPM_S0i3_3 = BIT(6),
: LPM_S0i3_4 = BIT(7),
: LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
: | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
: };
:
> do you see any users for these macros ? if not, then please drop
Hi Subrata, we will be using these macros to get supported lpm mask. This later will be used to set a UPD in FSP-S. Keeping the macro.
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/61f04481_89b47f87?us… :
PS72, Line 5: PTL_U_H_POWER_LIMITS
> as I could see from the doc 823589, […]
Hi Subrata, i have added the corresponding 15W/25W/45W into enum.
>Additionally, doc doesn't specify the PL2 value, rather it says that the PL2 is same as ARL-H on same segment. I don't know the PL2 value for ARL as well. Can you please help here. Unable to find PL4 as well in the doc.
I have used the override of Pl2, Pl4 settings from FSP.
File src/soc/intel/pantherlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/dc81fbaa_4733b062?us… :
PS72, Line 97: Lp4/
> I don't believe we support LP4 with PTL
Acknowledged
File src/soc/intel/pantherlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/0439f268_473d157e?us… :
PS72, Line 10: mainboard_update_premem_soc_chip_config
> who is the consumer of this code ?
Currently this use is depreciated. Removing.
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/0dcfc17d_fcd8c0ab?us… :
PS72, Line 26: /*TODO
> a space to start with […]
Acknowledged
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Attention is currently required from: Cliff Huang, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83635?usp=email
to look at the new patch set (#73).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,161 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/73
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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/espi.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/me.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
M src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/me.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
39 files changed, 3,685 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/23
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Change subject: mb/google/skyrim: Combine the function port_descriptors for variants
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Balaji Manigandan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83887?usp=email )
Change subject: Fix no-op for empty argument in Makefile for Bash compatibility
......................................................................
Fix no-op for empty argument in Makefile for Bash compatibility
This change addresses an issue encountered in Ubuntu 24.04 with GNU Bash
version 5.2.21, where the Makefile would fail with the error:
/bin/bash: -c: option requires an argument
make: *** [Makefile.mk:1440: build/coreboot.pre] Error 2
The error was triggered by an empty third argument `$(3)` in a conditional
`$(if ...)` statement. The original line did not specify an explicit no-op
for the case when `$(3)` is empty, which led to the execution of an incomplete
command.
By adding a colon `:` as a no-op command in the else-part of the `$(if ...)`,
we ensure that a harmless command is executed when `$(3)` is empty, preventing
the Makefile from failing due to a missing argument.
This fix ensures compatibility with the newer Bash version and prevents the
Makefile from breaking under the specified conditions.
Change-Id: I276e89792779832edf325d4f781aa8df101e9091
Signed-off-by: Manigandan, Balaji <balaji.manigandan(a)intel.com>
---
M Makefile.mk
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/83887/1
diff --git a/Makefile.mk b/Makefile.mk
index 901d6b2..0853c66 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -992,7 +992,7 @@
# non-empty if file removal requested)
define cbfs-add-cmd
printf " CBFS $(call extract_nth,2,$(1))\n"
- $(if $(3),-$(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null)
+ $(if $(3),-$(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null,:)
$(call cbfs-add-cmd-for-region,$(1),$(2))
endef
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Karthik Ramasubramanian has posted comments on this change by Morris Hsu. ( https://review.coreboot.org/c/coreboot/+/83874?usp=email )
Change subject: mb/google/brox/jubilant: Disable devcies and GPIOs by fw_config
......................................................................
Patch Set 7:
(2 comments)
File src/mainboard/google/brox/variants/jubilant/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83874/comment/4b8c3b3c_f9db6730?us… :
PS7, Line 3: STORAGE_UNKNOWN
It should be STORAGE_UNPROVISIONED and its value/mask should be 3.
https://review.coreboot.org/c/coreboot/+/83874/comment/a585f01b_19acc8df?us… :
PS7, Line 297: STORAGE_UNKNOWN
I think it should be STORAGE_UNPROVISIONED. An unprovisioned FW_CONFIG should be 0xffffffff. That should support first boot in factory. An unknown STORAGE means some part of FW_CONFIG is provisioned which is not correct.
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Eric Lai has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/83845?usp=email )
Change subject: mb/google/brya/var/nova: Enable TCSS XHCI setting
......................................................................
Patch Set 2: Code-Review+2
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Jakub Czapiga has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83886?usp=email )
Change subject: commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared error
......................................................................
Patch Set 2: Code-Review+2
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Hello Jakub Czapiga, Jon Murphy, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83886?usp=email
to look at the new patch set (#2).
Change subject: commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared error
......................................................................
commonlib/include: Include <stdint.h> to fix 'SIZE_MAX' undeclared error
This change includes the <stdint.h> header file to resolve the
compilation error "'SIZE_MAX' undeclared". This issue was introduced
by commit hash af0d4bce65df277b56e495892dff1c712ed76ddd (region:
Introduce region_create() functions).
TEST=Able to build google/rex.
Change-Id: I0dbd839e3573d5c74375911903c8f9d6a66bbf28
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/commonlib/include/commonlib/region.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83886/2
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