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Change subject: soc/intel/cnvi: Add CFLR Method
......................................................................
soc/intel/cnvi: Add CFLR Method
This method is used to limit frequencies on CNVi.
Intel document #559910 details this.
Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/common/block/cnvi/cnvi.c
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83712/6
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Change subject: soc/intel/cnvi: Add power related methods
......................................................................
soc/intel/cnvi: Add power related methods
Only the PRR method is used here, however, PS0, PS3 and DSM must
exist to avoid a BSOD on Windows.
Change-Id: Ib4a1a8a76ce74b991a3e8686e9594c2c2b145a39
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/soc/intel/common/block/cnvi/cnvi.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/83711/6
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Change subject: soc/intel/jasperlake: Add CrashLog implementation for Intel JSL
......................................................................
soc/intel/jasperlake: Add CrashLog implementation for Intel JSL
Extend support for CrashLog to Intel Jasperlake based platforms.
This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.
BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.
Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis(a)google.com>
---
M src/soc/intel/jasperlake/Makefile.mk
A src/soc/intel/jasperlake/crashlog_lib.c
A src/soc/intel/jasperlake/include/soc/crashlog.h
M src/soc/intel/jasperlake/include/soc/pci_devs.h
M src/soc/intel/jasperlake/romstage/fsp_params.c
M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h
6 files changed, 347 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/83884/2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 22:
(3 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/060d2b40_89eda6bc?us… :
PS12, Line 204: default 12
> Acknowledged
10 RPs for PTL-H (45W) and 12 RPs for PTL-UH as per EDS 815002
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83798/comment/cbef81d5_c6c36ca9?us… :
PS22, Line 243: TODO
give one space after `#`
File src/soc/intel/pantherlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/9f76b171_05514e5e?us… :
PS22, Line 11: 2
should be 4 and guard based on the PCH Kconfig.
if you are not keep on adding PTL-H (45W) support then keeping 4 alone will work for now.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 31:
(8 comments)
File src/soc/intel/pantherlake/acpi/pcie.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/fd602db3_b3ac859a?us… :
PS23, Line 237: Name (_ADR, 0x001D0000)
> Hi Subrata, we have reviwed this change to be corrected, but looks like the patch missed to add the changes. i have added the required correction.
I don't follow your argument here, these RP numbers were always wrong since patchset 1 of this CL and only correct with my code review. Therefore, I request to be more careful with the code change and try to be more meaningful.
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/4e61f1c3_e523f18b?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> Acknowledged
i would request to add a TODO so, we know that UFS ASL entry is pending.
Why don't you add things properly in this CL itself. You need one Kconfig which will be selected for PTL-U based boards alone and then include ufs.asl based on the same Kconfig
File src/soc/intel/pantherlake/acpi/tcss_dma.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/0ed1a030_ae9d117b?us… :
PS23, Line 9: Offset (0x85),
: PMEE, 1, /* 8, PME_EN */
> Done
do you know why it was added in the first place ? someone referred to the wrong EDS ?
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/05e9a108_93c52518?us… :
PS23, Line 56: 0xBAC
> Acknowledged
sorry, unable to follow. Why not use this CL and rather prefer to use another CL for converting harcoded values into macro ?
File src/soc/intel/pantherlake/acpi/tcss_pcierp.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/0db92d3b_7c05d0b1?us… :
PS31, Line 27:
still space and not tab
https://review.coreboot.org/c/coreboot/+/83772/comment/11bebdc0_e89a24cc?us… :
PS31, Line 28:
same
https://review.coreboot.org/c/coreboot/+/83772/comment/a97986ff_bc424f24?us… :
PS31, Line 29:
same
https://review.coreboot.org/c/coreboot/+/83772/comment/0b84ea59_6dc93705?us… :
PS31, Line 32: Offset (0x404),
: LSOE, 1,
: LNSE, 1,
same
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 72:
(6 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/ec1c3f89_0f7c413e?us… :
PS64, Line 108: 12
this is correct for PTL-UH
RP counts
1. PTL-UH - 12
2. PTL-H - 10
Please use PCH Kconfig to differentiate
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/87c85f1f_b9db0789?us… :
PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */
: enum lpm_state_mask {
: LPM_S0i2_0 = BIT(0),
: LPM_S0i2_1 = BIT(1),
: LPM_S0i2_2 = BIT(2),
: LPM_S0i3_0 = BIT(3),
: LPM_S0i3_1 = BIT(4),
: LPM_S0i3_2 = BIT(5),
: LPM_S0i3_3 = BIT(6),
: LPM_S0i3_4 = BIT(7),
: LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
: | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
: };
:
do you see any users for these macros ? if not, then please drop
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/e93db90f_a5f25d94?us… :
PS72, Line 5: PTL_U_H_POWER_LIMITS
as I could see from the doc 823589,
you might need to keep 3 macros
1. for PTL-U (15W)
2. for PTL-H (25W)
3. for PTL-H (45W)
an attempt to combine #1 and #2 won't work.
Additionally, doc doesn't specify the PL2 value, rather it says that the PL2 is same as ARL-H on same segment. I don't know the PL2 value for ARL as well. Can you please help here. Unable to find PL4 as well in the doc.
File src/soc/intel/pantherlake/include/soc/meminit.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/fc7d2b98_e9e24e4b?us… :
PS72, Line 97: Lp4/
I don't believe we support LP4 with PTL
File src/soc/intel/pantherlake/include/soc/romstage.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/7bb22104_0a987706?us… :
PS72, Line 10: mainboard_update_premem_soc_chip_config
who is the consumer of this code ?
File src/soc/intel/pantherlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83635/comment/0a210823_ac2b2166?us… :
PS72, Line 26: /*TODO
a space to start with
```
/* TODO: */
```
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