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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
Panther Lake U/H 12Xe/H 4Xe External Design
Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
Volume 2 of 2 #813030
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/include/soc/gpe.h
A src/soc/intel/pantherlake/include/soc/meminit.h
A src/soc/intel/pantherlake/include/soc/msr.h
A src/soc/intel/pantherlake/include/soc/pmc.h
A src/soc/intel/pantherlake/include/soc/romstage.h
A src/soc/intel/pantherlake/include/soc/soc_chip.h
A src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/meminit.c
A src/soc/intel/pantherlake/reset.c
A src/soc/intel/pantherlake/romstage/Makefile.mk
A src/soc/intel/pantherlake/romstage/fsp_params.c
A src/soc/intel/pantherlake/romstage/romstage.c
A src/soc/intel/pantherlake/romstage/systemagent.c
17 files changed, 1,134 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83635/72
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Jayvik Desai has posted comments on this change by Jayvik Desai. ( https://review.coreboot.org/c/coreboot/+/83705?usp=email )
Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
Patch Set 30:
(5 comments)
File src/vendorcode/google/chromeos/Kconfig:
https://review.coreboot.org/c/coreboot/+/83705/comment/4614e654_cdb7b45d?us… :
PS29, Line 109: criticial firmware updates on Chrome OS devices, particularly for
> > `'criticial' may be misspelled - perhaps 'critical'?` […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83705/comment/b8b201b8_4f13f199?us… :
PS29, Line 110:
> drop space
Acknowledged
https://review.coreboot.org/c/coreboot/+/83705/comment/f2e75a4a_a2b35983?us… :
PS29, Line 112:
> drop one empty line (just one is enough)
Acknowledged
https://review.coreboot.org/c/coreboot/+/83705/comment/d2cecf3c_f039d449?us… :
PS29, Line 115: -FSP uGOP: Closed-source solution from Intel's Firmware Support
> one space to start with after `-`
Acknowledged
https://review.coreboot.org/c/coreboot/+/83705/comment/9ca15ecd_6a0bf93f?us… :
PS29, Line 117: -
> same
Acknowledged
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Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik.
Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/adl: update libgx config to a generic eSOL config
......................................................................
soc/intel/adl: update libgx config to a generic eSOL config
This patch updates the early libgfx init config
(MAINBOARD_HAS_EARLY_LIBGFXINIT) used for Alder Lake SoC with a
generic CrOS/ChromeOS early sign of life config (CHROMEOS_ENABLE_ESOL)
This patch does not change the binary or the system behaviour and is
only meant to bind the early GFX initialization with a generic eSOL
config.
BUG=b:352651132
TEST=Able to build google/tivviks and checked the config in output
Change-Id: Ibc1b9190ac0e4d25f3c5517d74c9b519bc3bb349
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/alderlake/romstage/ux.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/83841/5
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Hello Andrey Petrov, Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
......................................................................
soc/intel/mtl: enable FSP uGOP config in MTL for eSOL
This patch updates the platform-specific Meteor Lake early
sign-of-life config (SOC_INTEL_METEORLAKE_SIGN_OF_LIFE) with a generic
ChromeOS eSOL config (CHROMEOS_ENABLE_ESOL) which uses the Intel FSP
uGOP driver as an underlying technology for rendering eSOL screen.
This patch does not change the binary or the system behaviour.
BUG=b:352651132
TEST=Able to build google/rex and checked the config in output.
Change-Id: Ib4589f52080229b1c83915b51272a042b7ac32cd
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
M src/soc/intel/meteorlake/romstage/fsp_params.c
2 files changed, 2 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/83769/25
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Change subject: vc/google/chromeos: Enable eSOL config with libgfx and uGOP
......................................................................
vc/google/chromeos: Enable eSOL config with libgfx and uGOP
This patch introduces a new early sign-of-life config option when
libgfx or uGOP is enabled for early graphics initialization.
BUG=b:352651132
TEST=Able to build google/rex and google/tivviks
Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950
Signed-off-by: Jayvik Desai <jayvik(a)google.com>
---
M src/vendorcode/google/chromeos/Kconfig
1 file changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/30
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Change subject: soc/intel/alderlake: Set UsbTcPortEn based on tcss_port[x]
......................................................................
Abandoned
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Change subject: profiler: Add basic profiler with cbmem support
......................................................................
Abandoned
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/riven: Add elan touchscreen support
......................................................................
mb/google/nissa/var/riven: Add elan touchscreen support
This change adds the necessary configuration for the elan
touchscreen (ELAN9004) device, connected to I2C bus 16.
It includes settings for:
* HID descriptor
* Device description
* IRQ configuration
* Detection
* Reset, stop and enable GPIOs with their respective delays
* Power resource handling
* HID descriptor register offset
BUG=b:348125053 b:348126380
TEST=emerge-nissa coreboot
boot with elan TS, make sure elan TS is functional.
Change-Id: I64c5a11dfaacfcca34240375d4dca5c76a60f62e
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/riven/overridetree.cb
1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/83876/3
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