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Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83752?usp=email )
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/6751366f_01b6ecb1?us… :
PS8, Line 365: BootFrequency
> By default it is set to 2 - i.e. turbo frequency
> We are setting it to 1 based on the inputs from PnP team
> According to their inputs - boot frequency set to 1 will not have any impact on performance once the system is booted up unlike PL values
I'm asking about MFIT CPU soft strap value. If that is set to 1 then CPU is booting at HFM. FSP UPD doesn't come to picture in such case
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Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/83752/comment/9a51e4d6_9330fd4a?us… :
PS8, Line 365: BootFrequency
> isn't this what we always set to 1 using MFIT CPU strap to enable system is booting in non-trulo max […]
By default it is set to 2 - i.e. turbo frequency
We are setting it to 1 based on the inputs from PnP team
According to their inputs - boot frequency set to 1 will not have any impact on performance once the system is booted up unlike PL values
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Hello Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelley Chen, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83752?usp=email
to look at the new patch set (#8).
Change subject: mb/google/brox: Fix booting to kernel without battery
......................................................................
mb/google/brox: Fix booting to kernel without battery
When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1.Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance. For boot with battery
increase PL1 min value to 15 watts.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/ramstage.c
M src/mainboard/google/brox/variants/brox/ramstage.c
M src/soc/intel/alderlake/romstage/fsp_params.c
3 files changed, 65 insertions(+), 105 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/83752/8
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Change subject: mb/google/brox: Do not override GPIO PM
......................................................................
Patch Set 1: Code-Review+2
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Change subject: drivers/soundwire: Support Realtek ALC722 codec
......................................................................
Patch Set 8:
(1 comment)
File src/drivers/soundwire/alc711/alc711.c:
https://review.coreboot.org/c/coreboot/+/81920/comment/c44eeb0e_3a8b416f?us… :
PS8, Line 23: ALC
> should we say Realtek ?
can you please take a look at this and then we can merge this CL?
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 73:
(3 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83635/comment/318789c2_1b23cd55?us… :
PS73, Line 45: SOC_INTEL_PANTHERLAKE_U_H
this is misleading,
there are 3 SoC flavours for PTL
1. PTL-U - 15W
2. PTL-H - 25W
3. PTL-H - 45W
now #1 and #2 are almost identical in usage of IOs (HSIO/LSIO) but #3 looks different hence, if you need different Kconfig to select between HSIO differences like 10 PCIe RP vs 12 PCIe RP then this Kconfig won't help.
lets use two Kconfig
1. SOC_INTEL_PANTHERLAKE_U_H (which cater to support both 15W and 25W SoC). I know the TDP would be different and for that we have enum already created to handle the chipset.cb PLx limits
2. SOC_INTEL_PANTHERLAKE_H (which only supports 45W SoC)
You can now use either #1 and #2 from above Kconfig to select the correct HSIO config.
Now Google/fatcat will select SOC_INTEL_PANTHERLAKE_U_H.
https://review.coreboot.org/c/coreboot/+/83635/comment/00242f17_4e798ee2?us… :
PS73, Line 269: SOC_INTEL_ACPI_GPIO_PINCTRL_COMPACT
I thought GPIO CL will introduce this Kconfig ?
File src/soc/intel/pantherlake/chipset.cb:
https://review.coreboot.org/c/coreboot/+/83635/comment/ef836ed2_4f0449a5?us… :
PS72, Line 5: PTL_U_H_POWER_LIMITS
> Hi Subrata, i have added the corresponding 15W/25W/45W into enum.
>
> >Additionally, doc doesn't specify the PL2 value, rather it says that the PL2 is same as ARL-H on same segment. I don't know the PL2 value for ARL as well. Can you please help here. Unable to find PL4 as well in the doc.
>
> I have used the override of Pl2, Pl4 settings from FSP.
may be you ensure the doc are being update, referring to FSP code is not ideal because not everyone has FSP source access.
please mark this after you are adding a TODO saying update the doc
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till romstage
......................................................................
Patch Set 73:
(1 comment)
File src/soc/intel/pantherlake/chip.h:
https://review.coreboot.org/c/coreboot/+/83635/comment/5fe8df54_fbd5b489?us… :
PS72, Line 63: /* Bit values for use in LpmStateEnableMask. */
: enum lpm_state_mask {
: LPM_S0i2_0 = BIT(0),
: LPM_S0i2_1 = BIT(1),
: LPM_S0i2_2 = BIT(2),
: LPM_S0i3_0 = BIT(3),
: LPM_S0i3_1 = BIT(4),
: LPM_S0i3_2 = BIT(5),
: LPM_S0i3_3 = BIT(6),
: LPM_S0i3_4 = BIT(7),
: LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2
: | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
: };
:
> Hi Subrata, we will be using these macros to get supported lpm mask. This later will be used to set a UPD in FSP-S. Keeping the macro.
If you need in this UPD for FSP-S then ideally it should be added as part of ramstage CL (isn't it ?)
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Attention is currently required from: Anil Kumar K, Naveen M, Paul Menzel.
Wonkyu Kim has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81920?usp=email )
Change subject: drivers/soundwire: Support Realtek ALC722 codec
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Patch Set 8: Code-Review+2
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