Yu-Ping Wu has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/83914?usp=email )
Change subject: commonlib/bsd/string: Fix pointer overflow for strnlen()
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/bsd/string.c:
https://review.coreboot.org/c/coreboot/+/83914/comment/ae002bdc_c4b0a99d?us… :
PS1, Line 19: str + maxlen + 1
> Upon closer inspection, my suggestion had the same problem of dereferencing one more byte than inten […]
Acknowledged
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Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83932?usp=email )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)
......................................................................
mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)
Locking GPP_F15 causes DUTs with fingerprint sensor to not be able to
correctly power down and stay powered down. This pin does not need to
be locked.
BUG=b:359692570, b:356750516
BRANCH=firmware-brya-14505.B
TEST=`FW_NAME=gimble emerge-brya coreboot chromeos-bootimage`, flash and
boot gimble into developer mode, then reboot into dev screen and select
the "Power off" button and verify gimble powers off and does not power
itself back up.
Change-Id: I1c73035b02021b0d1268cd46dcd0841621556ad5
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83932
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index 07f8dbd..9face2e 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -242,7 +242,7 @@
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PWROK, LEVEL, INVERT),
/* F15 : GSXSRESET# ==> FPMCU_INT_L */
- PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+ PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
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Nick Vaccaro has posted comments on this change by Nick Vaccaro. ( https://review.coreboot.org/c/coreboot/+/83932?usp=email )
Change subject: mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> With commit CB:64089, we now program the GPE Enable bit for all SCI pins during boot. […]
GPE status just before handing control off to libpayload (just before returning from bs_write_table() ):
```
[DEBUG] GPE0 STD STS: eSPI
```
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83905?usp=email )
Change subject: mb/google/dedede/var/awasuki: Enable HECI 1
......................................................................
mb/google/dedede/var/awasuki: Enable HECI 1
The AP console log contains "HECI: No CSE device" and the system cannot be entered.
BUG=b:359474142
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
The "HECI: No CSE device" message for AP log disappered
Change-Id: I488056dc8bca2174dd96c28793e3202b7aae890c
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83905
Reviewed-by: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/dedede/variants/awasuki/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
Tongtong Pan: Looks good to me, but someone else must approve
Karthik Ramasubramanian: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
index 148840f..5c85f50 100644
--- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb
@@ -203,7 +203,6 @@
end
end # I2C 2
device pci 15.3 off end # I2C 3
- device pci 16.0 off end # HECI 1
device pci 19.0 on
chip drivers/i2c/rt5645
register "hid" = ""10EC5650""
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83893?usp=email )
Change subject: Revert "mb/starlabs/starbook/adl: Update the VBT"
......................................................................
Revert "mb/starlabs/starbook/adl: Update the VBT"
This reverts commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8.
Reason for revert: The latest release of FSP will not boot
without a display being connected using this VBT. The original
VBT does not have this issue, nor is the original issue that
commit 2eb5c1e83ef5206f384846d7514c3aebcaec5bb8 fixed.
Revert it to restore booting when there is no display.
Change-Id: I05f9037cd68b8b29e69156e2372a544985f4442e
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83893
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/starlabs/starbook/variants/adl/data.vbt
1 file changed, 0 insertions(+), 0 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
Elyes Haouas: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/variants/adl/data.vbt b/src/mainboard/starlabs/starbook/variants/adl/data.vbt
index 8ecfffb..2c7db18 100644
--- a/src/mainboard/starlabs/starbook/variants/adl/data.vbt
+++ b/src/mainboard/starlabs/starbook/variants/adl/data.vbt
Binary files differ
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74619?usp=email )
Change subject: include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
......................................................................
include/cpu/amd/mtrr: rename TOP_MEM(2) and remove workaround
Both AGESA.h and cpu/amd/mtrr.h defined TOP_MEM and TOP_MEM2, but since
it was defined as unsigned long in AGESA.h, a workaround was needed in
cpu/amd/mtrr.h to not have the build fail due to a non-identical
redefinition of TOP_MEM and TOP_MEM2. Just removing the workaround
without reaming the defines isn't trivially possible, since the
stoneyridge romstage.c still ends up including both definitions which
can't be easily worked around. Now all non-vendorcode coreboot code uses
TOP_MEM_MSR and TOP_MEM2_MSR while the vendorcode part uses TOP_MEM and
TOP_MEM2 to avoid this.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ibad72dac17bd0b05734709d42c6802b7c8a87455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74619
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
---
M src/drivers/amd/agesa/s3_mtrr.c
M src/include/cpu/amd/mtrr.h
2 files changed, 6 insertions(+), 11 deletions(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index b085b4d..64a51ad 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -38,8 +38,8 @@
MTRR_PHYS_BASE(7),
MTRR_PHYS_MASK(7),
SYSCFG_MSR,
- TOP_MEM,
- TOP_MEM2,
+ TOP_MEM_MSR,
+ TOP_MEM2_MSR,
};
void backup_mtrr(void)
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 32a7949..9a60f3c 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -30,13 +30,8 @@
#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
-#if defined(__ASSEMBLER__)
-#define TOP_MEM 0xC001001A
-#define TOP_MEM2 0xC001001D
-#else
-#define TOP_MEM 0xC001001Aul
-#define TOP_MEM2 0xC001001Dul
-#endif
+#define TOP_MEM_MSR 0xC001001A
+#define TOP_MEM2_MSR 0xC001001D
#if !defined(__ASSEMBLER__)
@@ -68,12 +63,12 @@
static inline uint32_t get_top_of_mem_below_4gb(void)
{
- return rdmsr(TOP_MEM).lo;
+ return rdmsr(TOP_MEM_MSR).lo;
}
static inline uint64_t get_top_of_mem_above_4gb(void)
{
- msr_t msr = rdmsr(TOP_MEM2);
+ msr_t msr = rdmsr(TOP_MEM2_MSR);
return (uint64_t)msr.hi << 32 | msr.lo;
}
#endif
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83908?usp=email )
Change subject: soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
......................................................................
soc/intel/xeon_sp/uncore_acpi: use is_dev_on_domain0 where possible
Replace 'is_domain0(dev_get_domain(dev))' with 'is_dev_on_domain0(dev)'
which is a helper function that does exactly the same, but slightly
simplifies the call.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8b0c52a9176288039e6414a09c3fe0662db79e4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83908
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu(a)intel.com>
Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Shuo Liu: Looks good to me, approved
build bot (Jenkins): Verified
Elyes Haouas: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 0b2b9f4..baffdd0 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -532,7 +532,7 @@
struct device *dev = NULL;
struct device *iommu0 = NULL;
while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) {
- if (is_domain0(dev_get_domain(dev))) {
+ if (is_dev_on_domain0(dev)) {
iommu0 = dev;
continue;
}
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Attention is currently required from: Fabian Groffen, Keith Hui.
Keith Hui has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email )
Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75137/comment/8d9c37da_6c552d1b?us… :
PS4, Line 30: drq 0x1a = 0x02
> After checking boardview and the SIO/PCH datasheets, I can confirm 0x1b must stay. […]
Done
https://review.coreboot.org/c/coreboot/+/75137/comment/9074800a_e6686927?us… :
PS4, Line 32: drq 0x2c = 0x00 # GP27, 3VSBSW#, No TSI
> After checking boardview and the SIO/PCH datasheets, I can confirm this must stay. […]
Done
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Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui.
Keith Hui has uploaded a new patch set (#5) to the change originally created by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM
......................................................................
mb/asus/p8z77-m: Remove settings to replicate OEM
With these settings enabled COM 1/UART A/serial port 1 gets blocked
right after the kernel boots. It no longer works or responds, which
actually means the Linux boot process gets stuck forever when configured
to write to ttyS0.
Not using these settings, I have not found any downside. Serial keeps
working, sensors still work, S3 suspend/resume works correctly.
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75137/5
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