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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/e7aa6459_87e8bcaa?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> > Acknowledged […]
Hi Subrata, i have added a TODO to add ufs.asl for PTL-U SKU.
To porperly manage this inclusion using SOC type Kconfig, we have to introduce a PTL-U type SOC. Let me know if we can do that.
Suggestion:
config SOC_INTEL_PANTHERLAKE_U
bool
depends on !SOC_INTEL_PANTHERLAKE_H
select SOC_INTEL_PANTHERLAKE_BASE
help
Choose this option if the mainboard is built using PTL-U 4 P-cores +0
E- cores + 4 LP E-cores +4 Xe-cores system-on-a-chip (SoC).
Note, PTL-U processor line is offered in a single package platform that
includes the Compute tile, the PCD tile, and the GFX tile on the same
package.
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Change subject: mb/google/fatcat: Add Panther Lake SOC support
......................................................................
Patch Set 99:
(1 comment)
Patchset:
PS98:
> Sure, we have to push the change 1st for handeling "DMI_BASE_SIZE" in soc/intel/common/block/acpi/ac […]
Hi, i have updated the change in https://review.coreboot.org/c/coreboot/+/83938/1
Please review.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/dptf.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,007 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/43
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 42:
(1 comment)
File src/soc/intel/pantherlake/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/aa6d9e1e_512fdc64?us… :
PS23, Line 5: INTC1041
> got it. I will change these to the following:
>
> INT3400 -> manager
> INT3403 -> generic
> INT3404 -> fan
sorry, I mean to say that you should move the macros here at SoC specific file for PTL (INTC10D4)
https://github.com/coreboot/coreboot/blob/main/src/soc/intel/meteorlake/inc…
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/5f6865ba_b1308fbf?us… :
PS17, Line 54: .port = PID_GPIOCOM0,
> sorry. my bad. typo Subrata:)
Sorry, I'm unable to follow what you mean by PTL requires PID numbers as word size compared to ADL-MTL. I could see all GPIO PIDs for PTL are byte width and not word width.
```
#define PID_GPIOCOM0 0x59
#define PID_GPIOCOM1 0x5A
#define PID_GPIOCOM3 0x5B
#define PID_GPIOCOM4 0x5C
#define PID_GPIOCOM5 0x5D
```
So far we are using cpu_port PID which is same as GPIO comm Port ID, for example: in Alder Lake, the port id for COMM_0 and cpu_port PID for COMM_0 are same. I have seen the same logic even in MTL as well.
```
[COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0,
.cpu_port = PID_CPU_GPIOCOM0,
```
Are you saying, in PTL, cpu_port PID and port ID won't point to same PID value, where port id is still byte width but cpu_port PID is word width ?
Coming to how are we using cpu_port PIDs? we are using cpu_port PIDs for programming the AUX PAD configuration. This is not specific TCSS or any IP. This is still points to the GPIO PIN/PAD hence, we are relying on the GPIO community PID for cpu_port while calling calc_bias_ctrl_reg_value(). Example below, we would need to know the cpu_port PID for USB-C0 AUX pins.
```
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
```
I'm not very clear what you mean by " It turns out that the port id is 16-bit in PTL.".
If the cpu_port IDs for GPIO banks would be word width then I suggest doing refactoring of the common code by adding a new Kconfig (SOC_INTEL_COMMON_BLOCK_GPIO_CPU_PORT_16BITS) to update the common code data structure. But before that, please help me to understand the delta that PTL is bringing.
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Cliff Huang has uploaded a new patch set (#42) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/dptf.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,008 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/42
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