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Change subject: soc/intel/ptl: Dump SoC QDF from report_platform_info in bootblock
......................................................................
soc/intel/ptl: Dump SoC QDF from report_platform_info in bootblock
This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info
to report_cpu_info to dump QDF information from bootblock.
Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/bootblock/report_platform.c
2 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83940/3
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Hello Bora Guvendik, Hannah Williams, Kapil Porwal, Pranava Y N, Raj Astekar, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
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Change subject: soc/intel/ptl: Dump SoC QDF from report_platform_info in bootblock
......................................................................
soc/intel/ptl: Dump SoC QDF from report_platform_info in bootblock
This enables SOC_QDF_DYNAMIC_READ_PMC and adds pmc_dump_soc_qdf_info
to report_cpu_info to dump QDF information from bootblock.
Change-Id: Iaf6f46cd9be831dde345c3b3728cd66145746d68
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/bootblock/report_platform.c
2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/83940/2
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Change subject: soc/intel/ptl: Dump SoC QDF from report_platform_info in bootblock
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/pantherlake/bootblock/report_platform.c:
https://review.coreboot.org/c/coreboot/+/83940/comment/1c146aa4_d8eae3a1?us… :
PS1, Line 217: pmc_dump_soc_qdf_info();
can you add this into `report_cpu_info` ?
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/df316758_4a7b2258?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> Hi Subrata, i have added a TODO to add ufs.asl for PTL-U SKU.
> To porperly manage this inclusion using SOC type Kconfig, we have to introduce a PTL-U type SOC. Let me know if we can do that.
> Suggestion:
> config SOC_INTEL_PANTHERLAKE_U
> bool
> depends on !SOC_INTEL_PANTHERLAKE_H
> select SOC_INTEL_PANTHERLAKE_BASE
It would be ideal for this Kconfig to select `SOC_INTEL_PANTHERLAKE_UH` and include any additional selections for the UFS Kconfig if we add one later. Because UFS is a PCI device, I don't believe we need a Kconfig guard to prevent the default from being added. However, we may require a Kconfig for passing FSP UPDs for UFS, while PTL-H (25W) may not have UFS enabled. However, if FSP is intelligent enough to include these things internally, I don't think we need to add another Kconfig to indicate whether we're building fatcat with PTL-UH or PTL-U.
> help
> Choose this option if the mainboard is built using PTL-U 4 P-cores +0
> E- cores + 4 LP E-cores +4 Xe-cores system-on-a-chip (SoC).
> Note, PTL-U processor line is offered in a single package platform that
> includes the Compute tile, the PCD tile, and the GFX tile on the same
> package.
as I have mentioned previously this is just base CLs and not everything is expected to land as part of these initial Cls. Please avoid adding more stuffs and make the review complicated
if you wish to add PTL-U (which not existed until next year sometime as I learn) what is the point of adding dedicated Kconfig. we will be still selecting PTL-UH SoC from fatcat.
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 43:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/512b05f7_48010e91?us… :
PS17, Line 54: .port = PID_GPIOCOM0,
> > sorry. my bad. typo Subrata:) […]
For constructing PCR addresses to access the register, 8-bit port id is used. When accessing from outside of PCD, 16bit is used the first byte is segment ID, followed by 8bit port id. For instance, for IOM to access GPIO registers, segment ID is needed for global routing, who's value is 0xf2. The 2nd set of PID defines is needed for cpu_port:
#define SEGMENTID_CHIPSET0 0xf2
#define PID16_CHIPSET0(x) ((SEGMENTID_CHIPSET0 << 8) | x)
#define PID16_GPIOCOM0 PID16_CHIPSET0(PID_GPIOCOM0)
#define PID16_GPIOCOM1 PID16_CHIPSET0(PID_GPIOCOM1)
#define PID16_GPIOCOM3 PID16_CHIPSET0(PID_GPIOCOM3)
#define PID16_GPIOCOM4 PID16_CHIPSET0(PID_GPIOCOM4)
#define PID16_GPIOCOM5 PID16_CHIPSET0(PID_GPIOCOM5)
The field has been changed in the typec AUX bias cntrl registers in PTL. The port id is now 16-bit.
15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO
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Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83939?usp=email )
Change subject: soc/intel/cmn/pmc: Add pmc_ipc to bootblock
......................................................................
soc/intel/cmn/pmc: Add pmc_ipc to bootblock
This adds pmc_ipc to bootblock if SOC_QDF_DYNAMIC_READ_PMC is enabled.
The good place to dump and report SoC QDF can be report_platform_info
in bootblock. QDF read is done by PMC IPC Command, so this adds pmc_ipc
to bootblock to enable calling pmc_dump_soc_qdf_info.
Change-Id: Id0391eae48fc53cd652acd09e6380ca6802eaf88
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/soc/intel/common/block/pmc/Makefile.mk
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/83939/1
diff --git a/src/soc/intel/common/block/pmc/Makefile.mk b/src/soc/intel/common/block/pmc/Makefile.mk
index e46d5ee..18e1253 100644
--- a/src/soc/intel/common/block/pmc/Makefile.mk
+++ b/src/soc/intel/common/block/pmc/Makefile.mk
@@ -7,5 +7,6 @@
smm-y += pmclib.c
verstage-y += pmclib.c
postcar-y += pmclib.c
+bootblock-$(SOC_QDF_DYNAMIC_READ_PMC) += pmc_ipc.c
ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c
endif
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Change subject: mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
- main board changes should be combined with main board cl
- .asl changes should be part of ASL CL
- iomap changes should be part of ramstage CL
File src/soc/intel/common/block/acpi/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/83938/comment/60db082a_0b368ba5?us… :
PS2, Line 294: #if DMI_BASE_SIZE
what is this ?
what you are trying here is like
```
#ifdef DMI_BASE_SIZE
#endif
```
Rather than doing this, you can define DMI_BASE_SIZE with zero value for PTL. and add a check here
```
#if DMI_BASE_SIZE != 0
/* DMI BAR _BAS will be updated in _CRS below according to
* B0:D0:F0:Reg.68h
*/
Memory32Fixed (ReadWrite, 0, DMI_BASE_SIZE, DMIB)
#endif
```
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Attention is currently required from: Kapil Porwal, Pranava Y N, Saurabh Mishra, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83938?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi
......................................................................
mb/google/fatcat: Update dsdt.asl to include soc/intel/ptl/acpi
Details:
- This patch adds soc acpi file entry in mainboard dsdt.asl
- PTL replaces DMI3 with SAF, to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE gaurd check is added in northbridge.asl
BUG=b:348678529
TEST=Able to build the google/fatcat and boot to bootblock stage
using Intel® Simics® Pre Silicon Simulation platform for PTL.
Change-Id: I284a1eba19c03008f3e57f1427a72affb2129a8b
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/mainboard/google/fatcat/dsdt.asl
M src/mainboard/google/fatcat/variants/fatcat/include/variant/gpio.h
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/pantherlake/include/soc/iomap.h
4 files changed, 38 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83938/2
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Gerrit-MessageType: newpatchset
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I284a1eba19c03008f3e57f1427a72affb2129a8b
Gerrit-Change-Number: 83938
Gerrit-PatchSet: 2
Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com>
Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com>
Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>