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Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass
BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/l2c_ops.c
M src/soc/mediatek/mt8196/soc.c
3 files changed, 49 insertions(+), 0 deletions(-)
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Change subject: soc/mediatek: Refactor mmu operation for L2C SRAM and DMA
......................................................................
soc/mediatek: Refactor mmu operation for L2C SRAM and DMA
Refactor mmu operation by
- Move mtk_soc_disable_l2c_sram to l2c_ops.c
- Keep mtk_soc_after_dram in mmu_cmops.c
Change-Id: I14bd8a82e0b5f8f00ce2b52e5aee918e130912d4
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
A src/soc/mediatek/common/l2c_ops.c
M src/soc/mediatek/common/mmu_cmops.c
M src/soc/mediatek/mt8186/Makefile.mk
M src/soc/mediatek/mt8188/Makefile.mk
M src/soc/mediatek/mt8192/Makefile.mk
M src/soc/mediatek/mt8195/Makefile.mk
6 files changed, 39 insertions(+), 36 deletions(-)
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Change subject: soc/mediatek/mt8196: Add GPIO driver
......................................................................
soc/mediatek/mt8196: Add GPIO driver
Add GPIO driver for other modules to control GPIO pins.
TEST=build pass
BUG=b:317009620
Change-Id: I6d1e6ef17660308c8de908697ffba6b5f17ff9ae
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/gpio.c
A src/soc/mediatek/mt8196/include/soc/gpio.h
A src/soc/mediatek/mt8196/include/soc/gpio_base.h
4 files changed, 1,301 insertions(+), 0 deletions(-)
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
soc/mediatek/mt8196: Add NOR-Flash support
Add NOR-Flash drivers for flash read/write.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91
Signed-off-by: Noah Shen <noah.shen(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Kconfig
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/spi.h
M src/soc/mediatek/mt8196/spi.c
4 files changed, 47 insertions(+), 0 deletions(-)
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Change subject: soc/mediatek/mt8196: Fix timer reset in BL31
......................................................................
soc/mediatek/mt8196: Fix timer reset in BL31
1. Set systimer compensation to version 2.0.
2. The system does not need to serve pending IRQ from systimer
after rebooting. Therefore we clear systimer IRQ pending bit
at early booting.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/timer.h
M src/soc/mediatek/mt8196/timer.c
A src/soc/mediatek/mt8196/timer_prepare.c
4 files changed, 62 insertions(+), 3 deletions(-)
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Change subject: soc/mediatek/mt8196: Add I2C driver support
......................................................................
soc/mediatek/mt8196: Add I2C driver support
Add I2C controller drivers.
TEST=build pass
BUG=317009620
Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e
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---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/i2c.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/i2c.h
4 files changed, 303 insertions(+), 1 deletion(-)
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Change subject: mb/google/brox/jubilant: Update fw_config
......................................................................
mb/google/brox/jubilant: Update fw_config
Change STORAGE_UNPROVISIONED to STORAGE_UNKNOWN depend on depthcharge setting.
BUG=None
TEST=emerge-brox coreboot
Set STORAGE_UNKNOWN on jubilant, check that NVMe and UFS can boot.
Change-Id: I4cfd7322c2940862dfbae46e85522715cd7534c1
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---
M src/mainboard/google/brox/variants/jubilant/fw_config.c
M src/mainboard/google/brox/variants/jubilant/overridetree.cb
M src/mainboard/google/brox/variants/jubilant/variant.c
3 files changed, 6 insertions(+), 6 deletions(-)
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 35:
(1 comment)
Patchset:
PS35:
Use this CL before ACPI CL to that the iomap.h entries are getting auto resolved for ACPI code need.
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Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................
Patch Set 44:
(1 comment)
File src/soc/intel/pantherlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/83789/comment/87dc7caf_74ed51fe?us… :
PS17, Line 54: .port = PID_GPIOCOM0,
> For constructing PCR addresses to access the register, 8-bit port id is used. When accessing from outside of PCD, 16bit is used the first byte is segment ID, followed by 8bit port id. For instance, for IOM to access GPIO registers, segment ID is needed for global routing, who's value is 0xf2. The 2nd set of PID defines is needed for cpu_port:
>
> #define SEGMENTID_CHIPSET0 0xf2
> #define PID16_CHIPSET0(x) ((SEGMENTID_CHIPSET0 << 8) | x)
> #define PID16_GPIOCOM0 PID16_CHIPSET0(PID_GPIOCOM0)
> #define PID16_GPIOCOM1 PID16_CHIPSET0(PID_GPIOCOM1)
> #define PID16_GPIOCOM3 PID16_CHIPSET0(PID_GPIOCOM3)
> #define PID16_GPIOCOM4 PID16_CHIPSET0(PID_GPIOCOM4)
> #define PID16_GPIOCOM5 PID16_CHIPSET0(PID_GPIOCOM5)
>
>
>
> The field has been changed in the typec AUX bias cntrl registers in PTL. The port id is now 16-bit.
>
> 15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
> 18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
> 31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO
what you have explained is the SoC internal logic to access IPs across the Die. But here AP FW running as part of Host CPU should be able to access GPIO controllers in the same manner as Port ID 8-bit address. I don't see any need to change that. If IOM FW is accessing GPIO controllers then it needs to create the address with 16-bit PID because of outside of the die access.
Btw, I thought TCSS is also part of PCD die (unlike MTL where we had IOE die) hence, I'm not sure if I follow what you mean by "accessing outside PCD die"? Both GPIO and TCSS are part of the PCD die isn't it ?
looks like you are saying, the cpu_port will use some internal logic now while programming the GPIO controller hence, we need to support 16-bit cpu_port. If that is the case, then please follow my advice of adding a Kconfig which is true for PTL and then
can you please help me to understand the register big definition difference between
PTL:
```
15:0 RW 0x0 GROUP_ID Group ID in PCH GPIO; targeted SB_PORTID
18:16 RW 0x0 BIT_NUM Data bit Position in PCH GPIO
31:24 RW 0x0 VW_INDEX VW Index in PCH GPIO
```
and previous generations?
wondering if "GROUP_ID Group ID in PCH GPIO" was 8-bit previously ? I don't find this into the EDS.
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