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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/63552?usp=email )
Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/4f718f94_37df31c8?us… :
PS4, Line 37: SMI handler
> This is intended to be a temporary workaround until we have a permanent solution/workaround from Intel. We suspect the permanent solution will end up in the ADL-P chipset blob collateral (i.e. not FSP), but don't know for sure yet, and this should be able to be reverted later.
>
> _PTS may work, would have to test that there are no additional operations that happen after that runs to change the IP state again.
we don't have any solid W/A in FW space as Intel ack the issue for all ADL devices. The kernel fix implemented but we are still seeing this issue while performing poweroff before OS (and on consecutive boot, we are running into PMC IPC timeout issue)
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Change subject: mb/goog/brya: Don't lock GPP_F15 (FPMCU_INT_L)
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS3:
> GPE status just before handing control off to libpayload (just before returning from bs_write_table() ):
> ```
> [DEBUG] GPE0 STD STS: eSPI
> ```
Here is my observation:
1. Locking a PAD configured as GPE is the reason for the auto boot after system enter into S5.
2. I have dumped the GPE status before issuing poweroff from depthcharge screen.
```
Exiting depthcharge with code 2 at timestamp: 21490780
Powering off...
GPE0_STS_31_0 = 0
GPE0_STS_63_32 = 20804
GPE0_STS_95_64 = 64000 <----- GPP_F14 GPE Status is set
(GPE0_STS[127:96] = 4000
GPE0_EN_31_0 = 0
GPE0_EN_63_32 = 0
GPE0_EN_95_64 = 4000 <----- GPP_F14 GPE Enable is set
(GPE0_EN[127:96] = 0
```
GPE 78 aka GPP_F14 (touchpad) has GPE configured as GPE Enable and at the same time GPE status for this PAD is also set. Resulted in a auto wake after I issued poweroff at dev screen.
While waking the device from S5->S0, due to lack of XHCI W/A present into the mainline, I have experienced bunch of PMC IPC errors and eventually device booted to OS, where I can see GPE 78 as wake source (as guessed from the above log).
```
10 | 2024-08-15 14:25:56-0700 | ACPI Wake | S5
11 | 2024-08-15 14:25:56-0700 | Wake Source | GPE # | 78 <---- this is GPP_F14
12 | 2024-08-15 14:25:56-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown
```
3. Resolution: aviod configurating the lock for GPE so, that we are able to clear the GPE status in order to avoid fake wake.
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Saurabh Mishra has uploaded a new patch set (#46) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF, to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE gaurd check is added in northbridge.asl
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/dptf.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
13 files changed, 2,011 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/46
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Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
Patch Set 7: Code-Review+1
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Change subject: soc/mediatek: Refactor mmu operation for L2C SRAM and DMA
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Patch Set 5: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
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Patch Set 5: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add GPIO driver
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Patch Set 4: Code-Review+2
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Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
Patch Set 7:
(2 comments)
File src/soc/mediatek/mt8196/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83925/comment/0ac40903_cddc5ef4?us… :
PS7, Line 16: l2c_ops.c
move to above line ?
https://review.coreboot.org/c/coreboot/+/83925/comment/95f79569_023d2e3f?us… :
PS7, Line 19: l2c_ops.c
move to above line ?
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Change subject: soc/mediatek: Refactor mmu operation for L2C SRAM and DMA
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Patch Set 5: Code-Review+2
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