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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), ot_hao.han(a)mediatek.com,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8196: Add I2C driver support
......................................................................
soc/mediatek/mt8196: Add I2C driver support
Add I2C controller driver.
TEST=build pass
BUG=317009620
Change-Id: I617ad8a43ce8b492b1a0e5dc06c1f0ffe7d92b5e
Signed-off-by: ot_hao.han(a)mediatek.corp-partner.google.com
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/i2c.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/i2c.h
4 files changed, 303 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/83927/8
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Hello Hung-Te Lin, Xi Chen, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
......................................................................
soc/mediatek/mt8196: Enable mmu operation for L2C SRAM and DMA
- Turn off L2C SRAM and reconfigure as L2 cache:
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
- Configure DMA buffer in DRAM:
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass
BUG=b:317009620
Change-Id: I6a3cb63d3418f085f5d8d08b282dd59ea431c294
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
A src/soc/mediatek/mt8196/l2c_ops.c
M src/soc/mediatek/mt8196/soc.c
3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83925/8
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/23f853c6_0410fd8d?us… :
PS4, Line 37: SMI handler
> Ok, I guess if this is a general issue, it should be done in soc/intel/ code?
The SoC bug is generic, but its manifestation might be specific to CrOS. For example, the PMC IPC timeout that we are seeing is a dedicated command that only CrOS sends to the SoC. If the XHCI controller is in deep sleep or some U2 state (hung due to the SoC bug), it will ignore this command and result into timeout.
Windows devices use a different implementation of PDC to PMC communication that does not generate this IPC timeout error. Hope it clarifies why I'm still implementing the W/A in CrOS mainboard.
> But I understand why this needs to be done in SMM. If somebody pushes the power
> button early, they would expect a clean state.
>
> Paul, this was originally your thread. I'm closing it now, feel free to re-open
> if necessary.
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 6:
(2 comments)
Patchset:
PS6:
Adding some more ADL using devs in CC that may also be affected.
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/1721c63f_b769538a?us… :
PS4, Line 37: SMI handler
> > This is intended to be a temporary workaround until we have a permanent solution/workaround from I […]
Ok, I guess if this is a general issue, it should be done in soc/intel/ code?
But I understand why this needs to be done in SMM. If somebody pushes the power
button early, they would expect a clean state.
Paul, this was originally your thread. I'm closing it now, feel free to re-open
if necessary.
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/8d3abc69_ac80ae0f?us… :
PS4, Line 37: SMI handler
> > This is intended to be a temporary workaround until we have a permanent solution/workaround from Intel. We suspect the permanent solution will end up in the ADL-P chipset blob collateral (i.e. not FSP), but don't know for sure yet, and this should be able to be reverted later.
> >
> > _PTS may work, would have to test that there are no additional operations that happen after that runs to change the IP state again.
>
> we don't have any solid W/A in FW space as Intel ack the issue for all ADL devices. The kernel fix implemented but we are still seeing this issue while performing poweroff before OS (and on consecutive boot, we are running into PMC IPC timeout issue)
looks like we need this CL to ensure we are booting CrOS devices after poweroff at payload/depthcharge. We have few ADL devices that are running still running from mainline (not yet branched out).
Marking this resolved and hoping we can land FW W/A as there is no other solution to fix the SoC bug for ADL devices.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/5ca35aba_f6eaf083?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> Understood, valid points.
> Although, instead of using now a soc Kconfig, can we use "is_devfn_enabled(PCI_DEVFN_UFS)", this should also suffice the UPDs fill based on if UFS is enabled in Dervice Tree.
That is only possible if Intel is going to maintain UFS UPD for both PTL-UH and PTL-H. What if UFS UPDs are not present for PTL-H FSP header then we need to apply some kind of CPP to avoid compilation issue.
>
> Just a thought.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/c0fb3525_8054bfa3?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> > Ok sure, got the point. […]
Understood, valid points.
Although, instead of using now a soc Kconfig, can we use "is_devfn_enabled(PCI_DEVFN_UFS)", this should also suffice the UPDs fill based on if UFS is enabled in Dervice Tree.
Just a thought.
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/0c1faac6_531316e9?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> Ok sure, got the point.
> So, you are suggesting to guard USF asl inclusion using "SOC_INTEL_PANTHERLAKE_U_H" , for initial commit once the IP is exposed.
ACPI devices require guarding because they are soft devices and won't be able to sense if the device is present or not. All PCI devices don't even need the guarding because during probing the PCI device won't bind if the UFS controller is not present in the PCI bus.
Assuming UFS only existed for PTL-U in the future and not for PTL-H (25W), things will even work without introducing a new Kconfig and need to implement CPP for ACPI code. I'm guessing we may only need Kconfig to override UFS UPDs if FSP logic doesn't account for the fact that UFS UPDs are not applicable for PTL-H (25W). If FSP is able to dynamically handle UFS UPDs even for PTL-H (25W), we are assuming that we are enabling UFS UPDs default enable for PTL-UH (while UFS is only applicable for PTL-U and not for PTL-H).
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/acpi/southbridge.asl:
https://review.coreboot.org/c/coreboot/+/83772/comment/cfd703f1_1dfbd583?us… :
PS23, Line 47: /* UFS 0:17:0 */
: #include "ufs.asl"
> > Hi Subrata, i have added a TODO to add ufs.asl for PTL-U SKU. […]
Ok sure, got the point.
So, you are suggesting to guard USF asl inclusion using "SOC_INTEL_PANTHERLAKE_U_H" , for initial commit once the IP is exposed.
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