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Change subject: libpayload: Allow LTO with clang
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/84012/comment/1cdcdbc9_fdfbe283?us… :
PS1, Line 89: final binary size, but may increase compilation time.
> WDYT?
My intuition is still rather blank wrt. LTO. I guess it's not worth the hassle,
libpayload isn't used that much and people usually know that LTO it can be
tricky. Also who'd actually read the help text?
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Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#40).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
38 files changed, 3,584 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/40
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Change subject: libpayload: Allow LTO with clang
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/84012/comment/339183a8_ce35ec9d?us… :
PS1, Line 89: final binary size, but may increase compilation time.
> > How well is this tested with clang? Should we leave a warning?
>
> hackily. Clang forwards the actual linking to /usr/bin/gcc for some reason. So if you add -fuse-ld=lld and have a compatible version installed then it works.
>
> coreinfo with clang and lto does work.
>
> WDYT?
https://discourse.llvm.org/t/clang-linker-frontend-forwards-linking-to-gcc-… FYI
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Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Saurabh Mishra.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83798?usp=email
to look at the new patch set (#39).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
38 files changed, 3,571 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/39
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Saurabh Mishra has uploaded a new patch set (#49) to the change originally created by Ravishankar Sarawadi. ( https://review.coreboot.org/c/coreboot/+/83772?usp=email )
The following approvals got outdated and were removed:
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Change subject: soc/intel/ptl: Add SoC ACPI directory for Panther Lake
......................................................................
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF, to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE gaurd check is added in northbridge.asl
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/acpi/camera_clock_ctl.asl
A src/soc/intel/pantherlake/acpi/hda.asl
A src/soc/intel/pantherlake/acpi/pcie.asl
A src/soc/intel/pantherlake/acpi/serialio.asl
A src/soc/intel/pantherlake/acpi/southbridge.asl
A src/soc/intel/pantherlake/acpi/tcss.asl
A src/soc/intel/pantherlake/acpi/tcss_dma.asl
A src/soc/intel/pantherlake/acpi/tcss_pcierp.asl
A src/soc/intel/pantherlake/acpi/tcss_xhci.asl
A src/soc/intel/pantherlake/acpi/xhci.asl
12 files changed, 2,003 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/83772/49
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Arthur Heymans has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/84012?usp=email )
Change subject: libpayload: Allow LTO with clang
......................................................................
Patch Set 1:
(1 comment)
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/84012/comment/f7d19c30_c708d18c?us… :
PS1, Line 89: final binary size, but may increase compilation time.
> How well is this tested with clang? Should we leave a warning?
hackily. Clang forwards the actual linking to /usr/bin/gcc for some reason. So if you add -fuse-ld=lld and have a compatible version installed then it works.
coreinfo with clang and lto does work.
WDYT?
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Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/84029?usp=email )
Change subject: soc/mediatek/mt8196: Add MCUPM firmware v1.0
......................................................................
soc/mediatek/mt8196: Add MCUPM firmware v1.0
Add mcupm.bin initial version
TEST=NA
BUG=b:317009620
Change-Id: I639eb495e3499e0ed886368e6581031baaec0b9d
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M soc/mediatek/mt8196/README.md
A soc/mediatek/mt8196/mcupm.bin
A soc/mediatek/mt8196/mcupm.bin.md5
A soc/mediatek/mt8196/mcupm_release_notes.txt
4 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/29/84029/1
diff --git a/soc/mediatek/mt8196/README.md b/soc/mediatek/mt8196/README.md
index 19e17e3..bdc850b 100644
--- a/soc/mediatek/mt8196/README.md
+++ b/soc/mediatek/mt8196/README.md
@@ -1,9 +1,27 @@
# Firmware list
+- mcupm.bin
- sspm.bin
- dpm.dm
- dpm.pm
--------------------------------------------------------------------------------
+# MCUPM introduction
+MCUPM is a hardware module which is used for MCUSYS Power Management.
+MCUPM firmware (`mcupm.bin`) is loaded into MCUPM SRAM at system initialization.
+
+## Who uses it
+Coreboot will load MCUPM at ramstage. It will copy mcupm.bin to MCUPM SRAM.
+
+## How to load `mcupm.bin`
+Use CBFS to load `mcupm.bin`, then set normal boot flag and release software reset pin of MCUPM.
+
+## Return values
+No return value.
+
+## Version
+`$ strings mcupm.bin | grep "MCUPM firmware"`
+
+--------------------------------------------------------------------------------
# SSPM introduction
SSPM is "Secure System Power Manager" that provides power control in secure domain.
SSPM provides power related features, e.g. CPU DVFS, thermal control, to offload
diff --git a/soc/mediatek/mt8196/mcupm.bin b/soc/mediatek/mt8196/mcupm.bin
new file mode 100644
index 0000000..dbdf430
--- /dev/null
+++ b/soc/mediatek/mt8196/mcupm.bin
Binary files differ
diff --git a/soc/mediatek/mt8196/mcupm.bin.md5 b/soc/mediatek/mt8196/mcupm.bin.md5
new file mode 100644
index 0000000..74cb839
--- /dev/null
+++ b/soc/mediatek/mt8196/mcupm.bin.md5
@@ -0,0 +1 @@
+673fa9b1bb200ecc731b2b7d4f8cb0e5 mcupm.bin
diff --git a/soc/mediatek/mt8196/mcupm_release_notes.txt b/soc/mediatek/mt8196/mcupm_release_notes.txt
new file mode 100644
index 0000000..f3b09fd
--- /dev/null
+++ b/soc/mediatek/mt8196/mcupm_release_notes.txt
@@ -0,0 +1,4 @@
+** Build from MediaTek Internal **
+
+# Version 1.0
+1. Initial release.
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Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>