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Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 43:
(9 comments)
File src/soc/intel/pantherlake/chip.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/67d3abcd_de6ee35b?us… :
PS38, Line 139: /* Perform silicon specific init. */
> looks like you have skipped tbt_authentication and soc_enable_tracehub entries
Added.
https://review.coreboot.org/c/coreboot/+/83798/comment/df570ae4_4addd15b?us… :
PS38, Line 139: /* Perform silicon specific init. */
> looks like you have skipped tbt_authentication and soc_enable_tracehub entries
Added the entries.
File src/soc/intel/pantherlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/84fada37_a3a04bdb?us… :
PS38, Line 78: msr.lo |= (1 << 23); /* Lock it */
> wondering why did you overlooked https://review.coreboot. […]
Added.
File src/soc/intel/pantherlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/a5c3071a_44f10506?us… :
PS38, Line 15:
> please adopt 64-bit support for Crashlog like Intel added sometime back […]
Updated the crashlog as per MTL implementation & to adopt 64Bit.
https://review.coreboot.org/c/coreboot/+/83798/comment/91334600_b5302e6a?us… :
PS38, Line 59: u32
> this has been fixed in past using https://review.coreboot. […]
Updated the crashlog as per MTL implementation.
https://review.coreboot.org/c/coreboot/+/83798/comment/76824980_ea1d7a01?us… :
PS38, Line 59: u32
> this has been fixed in past using https://review.coreboot. […]
Updated the crsshlog
File src/soc/intel/pantherlake/include/soc/crashlog.h:
https://review.coreboot.org/c/coreboot/+/83798/comment/b4a7d95e_53a61ae1?us… :
PS38, Line 22:
> please follow https://review.coreboot. […]
Adopted the change as per ref. Cl shared.
https://review.coreboot.org/c/coreboot/+/83798/comment/4e516ce5_95e95973?us… :
PS38, Line 22:
> please follow https://review.coreboot. […]
Added.
File src/soc/intel/pantherlake/me.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/03ba57cc_9b3c3c54?us… :
PS38, Line 8:
> follow https://review.coreboot. […]
Updated, file removed.
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Change subject: soc/mediatek/common: Move GPIO definition to the common directory
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83988/comment/aada987c_5d09db03?us… :
PS3, Line 9: To reduce duplicate gpio definitions of MediaTek SoCs,
: move definitions to a common directory.
> ``` […]
Done
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Change subject: soc/mediatek/common: Print error if GPIO raw_id is not in the range
......................................................................
Patch Set 4:
(1 comment)
File src/soc/mediatek/common/gpio.c:
https://review.coreboot.org/c/coreboot/+/83987/comment/afd04e5a_e5a796ee?us… :
PS3, Line 197: if (!adv_info) {
: printk(BIOS_ERR, "%s: raw_id %u is out of range\n", __func__, gpio.id);
: return -1;
: }
> Are you sure we want to return -1 here? The original code seems to suggest that `adv_info` is option […]
Done
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Change subject: soc/mediatek/common: Print error if GPIO raw_id is not in the range
......................................................................
soc/mediatek/common: Print error if GPIO raw_id is not in the range
TEST=build pass
BUG=317009620
Change-Id: I5dffdb9f3e4e7e0d49209e6012893cd246948ee8
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/gpio.c
1 file changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/83987/4
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Change subject: soc/mediatek/common: Move GPIO definition to the common directory
......................................................................
soc/mediatek/common: Move GPIO definition to the common directory
To reduce duplicate gpio_base.h in each SoC folder, move gpio_base.h to
mediatek/common folder.
TEST=Build pass
BUG=b:317009620
Change-Id: I815df8a3083cf04b821165ec834ca98ee71a0c78
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
R src/soc/mediatek/common/include/soc/gpio_base.h
D src/soc/mediatek/mt8173/include/soc/gpio_base.h
D src/soc/mediatek/mt8183/include/soc/gpio_base.h
D src/soc/mediatek/mt8186/include/soc/gpio_base.h
D src/soc/mediatek/mt8188/include/soc/gpio_base.h
D src/soc/mediatek/mt8192/include/soc/gpio_base.h
6 files changed, 2 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/83988/4
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Change subject: soc/mediatek: Move SNFC pad_func into MediaTek common directory
......................................................................
soc/mediatek: Move SNFC pad_func into MediaTek common directory
To reduce duplicate pad_func of MediaTek SoCs,
Move the pad_fun to a common directory
TEST=Build pass
BUG=b:317009620
Change-Id: I145233ef887a38251e8fc129b8357f236c5f7a2b
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/common/flash_controller.c
M src/soc/mediatek/common/include/soc/flash_controller_common.h
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83989/4
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
soc/mediatek/mt8196: Add NOR-Flash support
Add NOR-Flash drivers for flash read/write.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: Id0a19f0520020f16c4cf9d62da4228a5b0371b91
Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Kconfig
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/spi.h
M src/soc/mediatek/mt8196/spi.c
4 files changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/83923/11
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Change subject: mb/google/rauru: Initialize flash controller in bootblock
......................................................................
mb/google/rauru: Initialize flash controller in bootblock
Initialize SPI NOR Flash Controller (SNFC) in the bootblock.
TEST=read nor flash data successfully.
BUG=b:317009620
Change-Id: I88960ce7a50f67ea6f402884b714cb205836a6d8
Signed-off-by: Noah Shen <noah.shen(a)mediatek.corp-partner.google.com>
---
M src/mainboard/google/rauru/Kconfig
M src/mainboard/google/rauru/bootblock.c
2 files changed, 6 insertions(+), 1 deletion(-)
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Change subject: soc/mediatek/mt8196: Fix timer reset in BL31
......................................................................
soc/mediatek/mt8196: Fix timer reset in BL31
1. Set systimer compensation to version 2.0.
2. The system does not need to serve pending IRQ from systimer
after rebooting. Therefore we clear systimer IRQ pending bit
at early booting.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/include/soc/timer.h
M src/soc/mediatek/mt8196/timer.c
A src/soc/mediatek/mt8196/timer_prepare.c
4 files changed, 62 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/83928/15
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