Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
Patch Set 46:
(1 comment)
File src/soc/intel/pantherlake/p2sb.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/c66f3b2f_a6d8c369?us… :
PS38, Line 45:
> you still need below code […]
Hi Subrata, is it still required to add p2sb2_read_resources & p2sb2_ops struct after changes made in patchset 46.
Please check and let me know.
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Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83798?usp=email
to look at the new patch set (#46).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
M src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
40 files changed, 3,512 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/46
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Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#45).
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
M src/soc/intel/pantherlake/chipset.cb
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
M src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
40 files changed, 3,779 insertions(+), 59 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/45
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Idc6fb11e9e84c28c7567ae2b7abc1ab832a88362
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
M src/soc/intel/pantherlake/Kconfig
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/acpi.c
A src/soc/intel/pantherlake/chip.c
M src/soc/intel/pantherlake/chip.h
A src/soc/intel/pantherlake/cpu.c
A src/soc/intel/pantherlake/crashlog.c
A src/soc/intel/pantherlake/cse_telemetry.c
A src/soc/intel/pantherlake/elog.c
A src/soc/intel/pantherlake/finalize.c
A src/soc/intel/pantherlake/fsp_params.c
A src/soc/intel/pantherlake/gspi.c
A src/soc/intel/pantherlake/i2c.c
A src/soc/intel/pantherlake/include/soc/cpu.h
A src/soc/intel/pantherlake/include/soc/crashlog.h
A src/soc/intel/pantherlake/include/soc/dptf.h
M src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/irq.h
A src/soc/intel/pantherlake/include/soc/itss.h
A src/soc/intel/pantherlake/include/soc/nvs.h
A src/soc/intel/pantherlake/include/soc/pcie.h
A src/soc/intel/pantherlake/include/soc/ramstage.h
A src/soc/intel/pantherlake/include/soc/serialio.h
M src/soc/intel/pantherlake/include/soc/systemagent.h
A src/soc/intel/pantherlake/include/soc/tcss.h
A src/soc/intel/pantherlake/include/soc/usb.h
A src/soc/intel/pantherlake/lockdown.c
A src/soc/intel/pantherlake/p2sb.c
A src/soc/intel/pantherlake/pcie_rp.c
A src/soc/intel/pantherlake/pmc.c
A src/soc/intel/pantherlake/pmutil.c
A src/soc/intel/pantherlake/retimer.c
A src/soc/intel/pantherlake/smihandler.c
A src/soc/intel/pantherlake/soundwire.c
A src/soc/intel/pantherlake/spi.c
A src/soc/intel/pantherlake/systemagent.c
A src/soc/intel/pantherlake/tcss.c
A src/soc/intel/pantherlake/uart.c
A src/soc/intel/pantherlake/xhci.c
39 files changed, 3,742 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83798/44
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Change subject: mb/google/rauru: Initialize flash controller in bootblock
......................................................................
Patch Set 11:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83924/comment/a449fd81_4307d834?us… :
PS10, Line 9: SPI
> Is this supposed to be "Serial" or "SPI"?
Serial Peripheral Interface = SPI
So, i think it's the same.
https://review.coreboot.org/c/coreboot/+/83924/comment/d186c1f7_a2e4b5f7?us… :
PS10, Line 9: (
> Space before `(`.
Done
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Change subject: soc/mediatek/mt8196: Add NOR-Flash support
......................................................................
Patch Set 11:
(2 comments)
File src/soc/mediatek/mt8196/include/soc/spi.h:
https://review.coreboot.org/c/coreboot/+/83923/comment/3d3cbb16_bd7de549?us… :
PS10, Line 12:
> Can we add a comment explaining what SNFC stands for (I found the term on https://www.mouser. […]
Done
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/83923/comment/3481a6ef_e065376a?us… :
PS10, Line 17: #define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func}
: #define PAD_FUNC_GPIO(name) {GPIO(name), 0}
> Not used
Done
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Gerrit-Comment-Date: Thu, 22 Aug 2024 11:10:16 +0000
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Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>