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Change subject: Documentation/vboot: Update vboot supported boards list
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Patch Set 1: Code-Review+2
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Change subject: Revert "mb/google/brya/var/xol: Change touchpad I2C interrupt type to GPIO_INT"
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Patch Set 1: Code-Review+2
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Change subject: cpu/x86: Don't do partial linking
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Patch Set 3:
(1 comment)
File src/cpu/x86/smm/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/84037/comment/46ae0aef_c2798623?us… :
PS3, Line 21: $(AR_smm) rcsT $@.tmp $(filter-out %.ld, $(smm-objs))
Why does it requires two steps ?
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Change subject: ext_stage_cache: Make sure variables are initialized
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Patch Set 7:
(1 comment)
File src/cpu/x86/smm/tseg_region.c:
https://review.coreboot.org/c/coreboot/+/84040/comment/533ab5e4_765e5839?us… :
PS7, Line 68: if (smm_subregion(SMM_SUBREGION_CACHE, (uintptr_t *)base, size)) {
You may as well remove the unnecessary brackets while you are at it.
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Hello Poornima Tom,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84060?usp=email
to look at the new patch set (#2).
Change subject: [skolas]: Add reference to wifi_sar_0.hex file
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[skolas]: Add reference to wifi_sar_0.hex file
Note: To test
Change-Id: Ic3bb2088f970e829f43a49e0e3497049eccf2b6d
Signed-off-by: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/skolas/variant.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/84060/2
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Change subject: cpu/x86/64bit: Compile and link separately
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Patch Set 1:
(1 comment)
File src/cpu/x86/64bit/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/84057/comment/4a0b38a1_50c8c5d5?us… :
PS1, Line 19: rm $@.o
Shouldn't we also delete the $@.tmp file created line 17 ?
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Change subject: car.ld: Fix bug with LLD
......................................................................
Patch Set 9:
(2 comments)
File src/arch/x86/car.ld:
https://review.coreboot.org/c/coreboot/+/84052/comment/f278761b_847e907e?us… :
PS9, Line 7: .car.fspm_rc_heap (CONFIG_DCACHE_RAM_BASE) (NOLOAD) : {
Wouldn't it make more sense to put that between line 13 and 14 ?
```
_car_region_start = CONFIG_DCACHE_RAM_BASE;
. = CONFIG_DCACHE_RAM_BASE;
.car.fspm_rc_heap (CONFIG_DCACHE_RAM_BASE) (NOLOAD) : {
. += CONFIG_FSP_M_RC_HEAP_SIZE;
}
.car.data . (NOLOAD) : {
[...]
```
https://review.coreboot.org/c/coreboot/+/84052/comment/89e6acf3_3ec5662a?us… :
PS9, Line 123: . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE;
It seems to be mostly used by sandybrige code with the following comment.
```
/*
* These are the location and structure of MRC_VAR data in CAR.
* The CAR region looks like this:
* +------------------+ -> DCACHE_RAM_BASE
* | |
* | |
* | COREBOOT STACK |
* | |
* | |
* +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE
* | |
* | MRC HEAP |
* | size = 0x5000 |
* | |
* +------------------+
* | |
* | MRC VAR |
* | size = 0x4000 |
* | |
* +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE
* + DCACHE_RAM_MRC_VAR_SIZE
*/
#define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \
+ CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000)
```
Since `. = _car_region_end;` is gone, how do we ensure we are at `DCACHE_RAM_BASE + DCACHE_RAM_SIZE` ?
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Change subject: mb/lenovo/thinkcentre_m710s: Drop PCH UPDs from PEG device
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> `lspci` seems to indicate that ASPM is enabled. […]
those are read from the config space of the bridge where the external pcie device is behind. my question is if ASPM still works on that slot of if the actual device in that slot just disappears. when there's something wrong with the clock and clock request pin config, the device behind the bridge might end up not getting out of L1
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