Maximilian Brune has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/81671?usp=email )
Change subject: util/crossgcc: Update ACPICA from 20230628 to 20240321
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Hello Felix Singer, build bot (Jenkins), Martin L Roth, Elyes Haouas,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/coreboot/+/83296?usp=email
to review the following change.
Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
......................................................................
Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc.
Reason for revert: The version downloaded does not match the version that is printed out when executing `iasl --version`. Coreboot notices that and refuses to compile QEMU-Q35 mainboard. I tested it on 2 different PCs.
Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468
TODO: Someone please confirm
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/acpica-unix-20230628_iasl.patch
A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
D util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
4 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83296/1
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index c35fc78..0691a5f2 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -40,7 +40,7 @@
MPC_VERSION=1.3.1
GCC_VERSION=13.2.0
BINUTILS_VERSION=2.42
-IASL_VERSION=20240321
+IASL_VERSION="20230628"
# CLANG version number
CLANG_VERSION=17.0.6
CMAKE_VERSION=3.29.3
@@ -74,7 +74,7 @@
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://downloadmirror.intel.com/819451"
+IASL_BASE_URL="https://downloadmirror.intel.com/783534"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…"
diff --git a/util/crossgcc/patches/acpica-unix-20240321_iasl.patch b/util/crossgcc/patches/acpica-unix-20230628_iasl.patch
similarity index 100%
rename from util/crossgcc/patches/acpica-unix-20240321_iasl.patch
rename to util/crossgcc/patches/acpica-unix-20230628_iasl.patch
diff --git a/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
new file mode 100644
index 0000000..9b676bb
--- /dev/null
+++ b/util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
@@ -0,0 +1 @@
+3b893fb771cf3fbd3531de3036e1a5bfc624c9d2 tarballs/acpica-unix-20230628.tar.gz
diff --git a/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
deleted file mode 100644
index e7b7afe..0000000
--- a/util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
+++ /dev/null
@@ -1 +0,0 @@
-19f5b03de6de059a95432d17ed24095262a97aba tarballs/acpica-unix-20240321.tar.gz
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Angel Pons has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/82494?usp=email )
Change subject: treewide: Add generation of CFR Tables
......................................................................
Patch Set 7:
(1 comment)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/82494/comment/cf212da8_af4ee30f?us… :
PS7, Line 568: __weak
> Then you have another weak function. […]
Well, this function would stop being weak. And weak no-op functions are "OK". Alternatively, don't provide an empty weak definition and introduce a Kconfig symbol to guard the `mainboard_update_sot_table()` function call.
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Change subject: treewide: Add generation of CFR Tables
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Patch Set 7:
(2 comments)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/82494/comment/fce927eb_008f8fec?us… :
PS7, Line 568: __weak
> What does Atlas need to do? If possible, I'd suggest having something like `void __weak mainboard_up […]
Then you have another weak function. But I see that having an extra specific `mainboard_*` weak function might be beneficial.
https://review.coreboot.org/c/coreboot/+/82494/comment/5ef55a40_079e00bc?us… :
PS7, Line 575: size_t size = cbfs_load("fallback/sot", sot_buf, MAX_SOT_SIZE);
> Is there a way to get the uncompressed size of a CBFS file at runtime? If so, it would be nice to us […]
I guess I could just use `cbfs_cbmem_alloc()`. Will try that.
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Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83269?usp=email )
Change subject: cpu/intel/model_206ax: Allow PL1/PL2 configuration
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83269/comment/afe7f342_ecb8985f?us… :
PS2, Line 9: Tested on ThinkPad T420 with the i7-3940XM.
> Can you please elaborate, how you tested this?
Set pl1=35000000 and pl2=43750000 microwatts in t420/devicetree.cb
Built and flashed
Confirmed power limits are 35000000 and 43750000 in sysfs intel-rapl-msr interface:
`$ cat /sys/devices/virtual/powercap/intel-rapl/intel-rapl:0/constraint_0_power_limit_uw`
and
`$ cat /sys/devices/virtual/powercap/intel-rapl/intel-rapl:0/constraint_1_power_limit_uw`
Also confirmed the same limits are applied in MCHBAR:
`$ MSR_PKG_POWER_LIMIT=0x610`
`$ MCH_PKG_POWER_LIMIT_LO=0xfed159a0`
`$ MCH_PKG_POWER_LIMIT_HI=0xfed159a4`
`$ sudo iotools mmio_read32 "${MCH_PKG_POWER_LIMIT_LO}"` => 0x00dc8118
`$ sudo iotools mmio_read32 "${MCH_PKG_POWER_LIMIT_LO}"` => 0x0000815e
`$ sudo rdmsr -c "${MSR_PKG_POWER_LIMIT}"` => 0x815e00dc8118
Finally, run stress test:
`$ stress-ng -c 8 --cpu-method matrixprod`
while monitoring processor package power using Intel PCM (https://github.com/intel/pcm)
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Change subject: mb/google/geralt: change config to FW_config for support TAS2563 audio amp
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83287/comment/36f78194_524018b4?us… :
PS8, Line 7: support TAS2563 audio amp
> You also change other logic, don’t you, that fw_config is used for `GERALT_USE_MAX98390`. […]
Done
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Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), cong yang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83287?usp=email
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The following approvals got outdated and were removed:
Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins)
Change subject: mb/google/geralt: change config to FW_config for support TAS2563 audio amp
......................................................................
mb/google/geralt: change config to FW_config for support TAS2563 audio amp
In order to support the judgment of FW_CONFIG, we change the config
GERALT_USE_MAX98390 to FW_CONFIG and add the relevant configuration
of devicetree. In addition, we delete the unused GERALT_USE_MAX98390.
BUG=b:345629159
BRANCH=none
TEST=emerge-GERALT coreboot
TEST=Verify beep function through deploy in depthcharge successfully.
Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab
Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/geralt/Kconfig
M src/mainboard/google/geralt/chromeos.c
M src/mainboard/google/geralt/devicetree.cb
M src/mainboard/google/geralt/mainboard.c
4 files changed, 21 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/83287/9
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Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
......................................................................
Patch Set 38: Code-Review-1
(1 comment)
Patchset:
PS38:
Talos II firmware enabled secure boot in 2.10 by default [1],
so this will no longer be enough. Created image should be signed
with all 3 HW keys as well as the OS key.
[1] https://wiki.raptorcs.com/wiki/Talos_II/Firmware/2.10/Release_Notes
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Change subject: treewide: Add generation of CFR Tables
......................................................................
Patch Set 7:
(2 comments)
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/82494/comment/48c459bf_45623fd7?us… :
PS7, Line 568: __weak
> There is a use case on the prodrive atlas baord, that needs to update the SOT tables in runtime (so […]
What does Atlas need to do? If possible, I'd suggest having something like `void __weak mainboard_update_sot_table(void *sot_buf, size_t size) {}` (empty weak definition) and call it from `write_sot_table()`.
https://review.coreboot.org/c/coreboot/+/82494/comment/55dd46d1_e5d026e2?us… :
PS7, Line 575: size_t size = cbfs_load("fallback/sot", sot_buf, MAX_SOT_SIZE);
Is there a way to get the uncompressed size of a CBFS file at runtime? If so, it would be nice to use it to avoid allocating and then deallocating stuff in CBMEM, as well as to log a more detailed error when SOT size exceeds `MAX_SOT_SIZE` (and by how much).
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