coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > The github release has got the correct version. The issue seems to come from the intel mirror. […] Oh I see we have only just recently switched to the intel mirror: CB:80721 (so I guess that is not an option then?) -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 01 Jul 2024 13:59:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Lean Sheng Tan, Werner Zeh. Hello Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83294?usp=email to look at the new patch set (#3). Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... 3rdparty/fsp: Update submodule to upstream master The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/fsp M src/soc/intel/elkhartlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/83294/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Gerrit-Change-Number: 83294 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Maximilian Brune has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/83296?usp=email ) Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: The github release has got the correct version. The issue seems to come from the intel mirror. So we could just switch to github for ACPICA. -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 01 Jul 2024 13:57:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: commonlib/bsd/lz4_wrapper.c: Fix misaligned access
by Felix Held (Code Review) 01 Jul '24

01 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email ) Change subject: commonlib/bsd/lz4_wrapper.c: Fix misaligned access ...................................................................... commonlib/bsd/lz4_wrapper.c: Fix misaligned access Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Make the compiler generate code that adheres to natural alignment by fixing the LZ4_readLE16() function and creating LZ4_readLE32(). Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Reviewed-on: https://review.coreboot.org/c/coreboot/+/81910 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/bsd/lz4_wrapper.c 1 file changed, 21 insertions(+), 7 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/commonlib/bsd/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c index efe246b..566c2bf 100644 --- a/src/commonlib/bsd/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -5,15 +5,29 @@ #include <commonlib/bsd/sysincludes.h> #include <stdint.h> #include <string.h> +#include <endian.h> -/* LZ4 comes with its own supposedly portable memory access functions, but they - * seem to be very inefficient in practice (at least on ARM64). Since coreboot - * knows about endianness and allows some basic assumptions (such as unaligned - * access support), we can easily write the ones we need ourselves. */ +/* + * RISC-V and older ARM architectures do not mandate support for misaligned access. + * Our le16toh and friends functions assume misaligned access support. Writing the access + * like this causes the compiler to generate instructions using misaligned access (or not) + * depending on the architecture. So there is no performance penalty for platforms supporting + * misaligned access. + */ static uint16_t LZ4_readLE16(const void *src) { - return le16toh(*(const uint16_t *)src); + return *((const uint8_t *)src + 1) << 8 + | *(const uint8_t *)src; } + +static uint32_t LZ4_readLE32(const void *src) +{ + return *((const uint8_t *)src + 3) << 24 + | *((const uint8_t *)src + 2) << 16 + | *((const uint8_t *)src + 1) << 8 + | *(const uint8_t *)src; +} + static void LZ4_copy8(void *dst, const void *src) { /* ARM32 needs to be a special snowflake to prevent GCC from coalescing the @@ -107,7 +121,7 @@ return 0; /* input overrun */ /* We assume there's always only a single, standard frame. */ - if (le32toh(h->magic) != LZ4F_MAGICNUMBER + if (LZ4_readLE32(&h->magic) != LZ4F_MAGICNUMBER || (h->flags & VERSION) != (1 << VERSION_SHIFT)) return 0; /* unknown format */ if ((h->flags & RESERVED0) || (h->block_descriptor & RESERVED1_2)) @@ -127,7 +141,7 @@ break; /* input overrun */ struct lz4_block_header b = { - .raw = le32toh(*(const uint32_t *)in) + .raw = LZ4_readLE32((const uint32_t *)in) }; in += sizeof(struct lz4_block_header); -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 7 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321"
by Maximilian Brune (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Elyes Haouas, Felix Singer, Martin L Roth. Hello Elyes Haouas, Felix Singer, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83296?usp=email to look at the new patch set (#2). Change subject: Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" ...................................................................... Revert "util/crossgcc: Update ACPICA from 20230628 to 20240321" This reverts commit 41fdb882f1f0c3cda41651c2e9c920580415a0dc. Reason for revert: The version downloaded does not match the version that is printed out when executing `iasl --version`. Coreboot notices that and refuses to compile QEMU-Q35 mainboard. I tested it on 2 different PCs. TODO: Someone please confirm Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20230628_iasl.patch A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum D util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum 4 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83296/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83296?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ce0c5798f14162eaa063a9a64e16e6dbbb9e468 Gerrit-Change-Number: 83296 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: drivers/spi/acpi: Add generic property list
by Felix Held (Code Review) 01 Jul '24

01 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83139?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/spi/acpi: Add generic property list ...................................................................... drivers/spi/acpi: Add generic property list The touchscreen vendor (Goodix) needs to use this value (hid-report-addr) in the touch driver, and this value needs to be changed later.So add generic property list to allow populating vendor specific device properties to ACPI SSDT table. BUG=b:342932183 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83139 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/spi/acpi/acpi.c M src/drivers/spi/acpi/chip.h 2 files changed, 9 insertions(+), 1 deletion(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c index 6d92776..687dd52 100644 --- a/src/drivers/spi/acpi/acpi.c +++ b/src/drivers/spi/acpi/acpi.c @@ -131,7 +131,7 @@ /* Write device properties if needed */ if (config->compat_string || irq_gpio_index >= 0 || - reset_gpio_index >= 0 || enable_gpio_index >= 0) { + reset_gpio_index >= 0 || enable_gpio_index >= 0 || config->property_count) { struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); if (config->compat_string) acpi_dp_add_string(dsd, "compatible", @@ -148,6 +148,9 @@ acpi_dp_add_gpio(dsd, "enable-gpios", path, enable_gpio_index, 0, config->enable_gpio.active_low); + /* Add generic property list */ + acpi_dp_add_property_list(dsd, config->property_list, + config->property_count); acpi_dp_write(dsd); } diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h index 9bee847..b7b39f7 100644 --- a/src/drivers/spi/acpi/chip.h +++ b/src/drivers/spi/acpi/chip.h @@ -5,6 +5,8 @@ #include <acpi/acpi_device.h> +#define MAX_GENERIC_PROPERTY_LIST 10 + struct drivers_spi_acpi_config { const char *hid; /* ACPI _HID (required) */ const char *cid; /* ACPI _CID */ @@ -42,6 +44,9 @@ unsigned int stop_delay_ms; /* Delay to be inserted after enabling stop. */ unsigned int stop_off_delay_ms; + /* Generic properties for exporting device-specific data to the OS */ + struct acpi_dp property_list[MAX_GENERIC_PROPERTY_LIST]; + unsigned int property_count; }; #endif /* __SPI_ACPI_CHIP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83139?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8b18e0a2925e6fd36e3a470bde9910661b7558b8 Gerrit-Change-Number: 83139 Gerrit-PatchSet: 11 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: soc/nvidia: Remove unneeded white spaces
by Felix Held (Code Review) 01 Jul '24

01 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83255?usp=email ) Change subject: soc/nvidia: Remove unneeded white spaces ...................................................................... soc/nvidia: Remove unneeded white spaces Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83255 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/sdram_lp0.c 4 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c index 3817dd9..8e9579c 100644 --- a/src/soc/nvidia/tegra124/power.c +++ b/src/soc/nvidia/tegra124/power.c @@ -8,8 +8,8 @@ #include <soc/pmc.h> #include <soc/power.h> -static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; -static struct flow_ctlr * const flow = (void *)TEGRA_FLOW_BASE; +static struct tegra_pmc_regs *const pmc = (void *)TEGRA_PMC_BASE; +static struct flow_ctlr *const flow = (void *)TEGRA_FLOW_BASE; static int partition_powered(int id) { diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index ef3c716..5361780 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -23,8 +23,8 @@ */ void sdram_lp0_save_params(const struct sdram_params *sdram) { - struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; - struct clk_rst_ctlr * clk_rst = (void *)TEGRA_CLK_RST_BASE; + struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; + struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c index 4968c85..4d74142 100644 --- a/src/soc/nvidia/tegra210/power.c +++ b/src/soc/nvidia/tegra210/power.c @@ -7,7 +7,7 @@ #include <soc/pmc.h> #include <soc/power.h> -static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; +static struct tegra_pmc_regs *const pmc = (void *)TEGRA_PMC_BASE; enum { POWER_GATE = 0, diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 5d65b2d..81402cd 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -12,7 +12,7 @@ */ void sdram_lp0_save_params(const struct sdram_params *sdram) { - struct tegra_pmc_regs * pmc = (void *)TEGRA_PMC_BASE; + struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ -- To view, visit https://review.coreboot.org/c/coreboot/+/83255?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd19cdcfbdf0b01984e0db0aa880fdcb256663b4 Gerrit-Change-Number: 83255 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel
by Felix Held (Code Review) 01 Jul '24

01 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83221?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel ...................................................................... mb/google/corsola/var/wugtrio: Add LCE_LMFBX101117480 MIPI panel Add LCE_LMFBX101117480 MIPI panel for Wugtrio. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/panel_wugtrio.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 6baaeac..41f9845 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -70,6 +70,7 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select MIPI_PANEL_KD_KD101NE3_40TI if BOARD_GOOGLE_WUGTRIO + select MIPI_PANEL_LCE_LMFBX101117480 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_ER88577 if BOARD_GOOGLE_WUGTRIO select MIPI_PANEL_STA_HIMAX83102_J02 if BOARD_GOOGLE_STARMIE select MIPI_PANEL_STA_ILI9882T if BOARD_GOOGLE_STARMIE diff --git a/src/mainboard/google/corsola/panel_wugtrio.c b/src/mainboard/google/corsola/panel_wugtrio.c index c8a8971..0603ce0 100644 --- a/src/mainboard/google/corsola/panel_wugtrio.c +++ b/src/mainboard/google/corsola/panel_wugtrio.c @@ -41,6 +41,14 @@ .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_RIGHT_UP, }, + /* LCE Corporation panel with bias IC on it */ + [7] = { + .configure_backlight = backlight_control, + .power_on = mipi_panel_power_on, + .name = "LCE_LMFBX101117480", + .disp_path = DISP_PATH_MIPI, + .orientation = LB_FB_ORIENTATION_RIGHT_UP, + }, }; struct panel_description *get_panel_description(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/83221?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad Gerrit-Change-Number: 83221 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: drivers/mipi: Add support for LCE_LMFBX101117480 panel
by Felix Held (Code Review) 01 Jul '24

01 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83220?usp=email ) Change subject: drivers/mipi: Add support for LCE_LMFBX101117480 panel ...................................................................... drivers/mipi: Add support for LCE_LMFBX101117480 panel Add STA panel LCE_LMFBX101117480 serializable data to CBFS. Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf About the init code, we communicated with the vendor through the datasheet to confirm the writing method of each register value. BUG=b:331870701 TEST=build and check the CBFS includes the panel BRANCH=None Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83220 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/drivers/mipi/Kconfig M src/drivers/mipi/Makefile.mk A src/drivers/mipi/panel-LCE_LMFBX101117480.c 3 files changed, 235 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Xuxin Xiong: Looks good to me, but someone else must approve Yidi Lin: Looks good to me, approved diff --git a/src/drivers/mipi/Kconfig b/src/drivers/mipi/Kconfig index 4f3257f..d70e92d 100644 --- a/src/drivers/mipi/Kconfig +++ b/src/drivers/mipi/Kconfig @@ -48,6 +48,9 @@ config MIPI_PANEL_KD_KD101NE3_40TI bool +config MIPI_PANEL_LCE_LMFBX101117480 + bool + config MIPI_PANEL_STA_2081101QFH032011_53G bool diff --git a/src/drivers/mipi/Makefile.mk b/src/drivers/mipi/Makefile.mk index 3890917..a71cff6 100644 --- a/src/drivers/mipi/Makefile.mk +++ b/src/drivers/mipi/Makefile.mk @@ -25,6 +25,8 @@ panel-params-$(CONFIG_MIPI_PANEL_KD_KD101NE3_40TI) += panel-KD_KD101NE3_40TI +panel-params-$(CONFIG_MIPI_PANEL_LCE_LMFBX101117480) += panel-LCE_LMFBX101117480 + panel-params-$(CONFIG_MIPI_PANEL_STA_2081101QFH032011_53G) += panel-STA_2081101QFH032011_53G panel-params-$(CONFIG_MIPI_PANEL_STA_ER88577) += panel-STA_ER88577 panel-params-$(CONFIG_MIPI_PANEL_STA_HIMAX83102_J02) += panel-STA_HIMAX83102_J02 diff --git a/src/drivers/mipi/panel-LCE_LMFBX101117480.c b/src/drivers/mipi/panel-LCE_LMFBX101117480.c new file mode 100644 index 0000000..4714017 --- /dev/null +++ b/src/drivers/mipi/panel-LCE_LMFBX101117480.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mipi/panel.h> + +struct panel_serializable_data LCE_LMFBX101117480 = { + .edid = { + .ascii_string = "LMFBX101117480", + .manufacturer_name = "LCE", + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .pixel_clock = 70595, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 800, .hbl = 90, .hso = 30, .hspw = 30, + .va = 1280, .vbl = 42, .vso = 30, .vspw = 4, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, + }, + .init = { + PANEL_DELAY(24), + PANEL_DCS(0xE0, 0x00), + PANEL_DCS(0xE1, 0x93), + PANEL_DCS(0xE2, 0x65), + PANEL_DCS(0xE3, 0xF8), + PANEL_DCS(0x80, 0x03), + PANEL_DCS(0xE0, 0x01), + PANEL_DCS(0x0C, 0x74), + PANEL_DCS(0x17, 0x00), + PANEL_DCS(0x18, 0xBF), + PANEL_DCS(0x19, 0x00), + PANEL_DCS(0x1A, 0x00), + PANEL_DCS(0x1B, 0xBF), + PANEL_DCS(0x1C, 0x00), + PANEL_DCS(0x1F, 0x70), + PANEL_DCS(0x20, 0x2D), + PANEL_DCS(0x21, 0x2D), + PANEL_DCS(0x22, 0x7E), + PANEL_DCS(0x24, 0xFE), + PANEL_DCS(0x37, 0x19), + PANEL_DCS(0x35, 0x28), + PANEL_DCS(0x38, 0x05), + PANEL_DCS(0x39, 0x08), + PANEL_DCS(0x3A, 0x12), + PANEL_DCS(0x3C, 0x78), + PANEL_DCS(0x3D, 0xFF), + PANEL_DCS(0x3E, 0xFF), + PANEL_DCS(0x3F, 0x7F), + PANEL_DCS(0x40, 0x06), + PANEL_DCS(0x41, 0xA0), + PANEL_DCS(0x43, 0x1E), + PANEL_DCS(0x44, 0x0B), + PANEL_DCS(0x0C, 0x74), + PANEL_DCS(0x55, 0x02), + PANEL_DCS(0x56, 0x01), + PANEL_DCS(0x57, 0x8E), + PANEL_DCS(0x58, 0x09), + PANEL_DCS(0x59, 0x0A), + PANEL_DCS(0x5A, 0x2E), + PANEL_DCS(0x5B, 0x1A), + PANEL_DCS(0x5C, 0x15), + PANEL_DCS(0x5D, 0x7F), + PANEL_DCS(0x5E, 0x69), + PANEL_DCS(0x5F, 0x59), + PANEL_DCS(0x60, 0x4E), + PANEL_DCS(0x61, 0x4C), + PANEL_DCS(0x62, 0x40), + PANEL_DCS(0x63, 0x45), + PANEL_DCS(0x64, 0x30), + PANEL_DCS(0x65, 0x4A), + PANEL_DCS(0x66, 0x49), + PANEL_DCS(0x67, 0x4A), + PANEL_DCS(0x68, 0x68), + PANEL_DCS(0x69, 0x57), + PANEL_DCS(0x6A, 0x5B), + PANEL_DCS(0x6B, 0x4E), + PANEL_DCS(0x6C, 0x49), + PANEL_DCS(0x6D, 0x24), + PANEL_DCS(0x6E, 0x12), + PANEL_DCS(0x6F, 0x02), + PANEL_DCS(0x70, 0x7F), + PANEL_DCS(0x71, 0x69), + PANEL_DCS(0x72, 0x59), + PANEL_DCS(0x73, 0x4E), + PANEL_DCS(0x74, 0x4C), + PANEL_DCS(0x75, 0x40), + PANEL_DCS(0x76, 0x45), + PANEL_DCS(0x77, 0x30), + PANEL_DCS(0x78, 0x4A), + PANEL_DCS(0x79, 0x49), + PANEL_DCS(0x7A, 0x4A), + PANEL_DCS(0x7B, 0x68), + PANEL_DCS(0x7C, 0x57), + PANEL_DCS(0x7D, 0x5B), + PANEL_DCS(0x7E, 0x4E), + PANEL_DCS(0x7F, 0x49), + PANEL_DCS(0x80, 0x24), + PANEL_DCS(0x81, 0x12), + PANEL_DCS(0x82, 0x02), + PANEL_DCS(0xE0, 0x02), + PANEL_DCS(0x00, 0x52), + PANEL_DCS(0x01, 0x55), + PANEL_DCS(0x02, 0x55), + PANEL_DCS(0x03, 0x50), + PANEL_DCS(0x04, 0x77), + PANEL_DCS(0x05, 0x57), + PANEL_DCS(0x06, 0x55), + PANEL_DCS(0x07, 0x4E), + PANEL_DCS(0x08, 0x4C), + PANEL_DCS(0x09, 0x5F), + PANEL_DCS(0x0A, 0x4A), + PANEL_DCS(0x0B, 0x48), + PANEL_DCS(0x0C, 0x55), + PANEL_DCS(0x0D, 0x46), + PANEL_DCS(0x0E, 0x44), + PANEL_DCS(0x0F, 0x40), + PANEL_DCS(0x10, 0x55), + PANEL_DCS(0x11, 0x55), + PANEL_DCS(0x12, 0x55), + PANEL_DCS(0x13, 0x55), + PANEL_DCS(0x14, 0x55), + PANEL_DCS(0x15, 0x55), + PANEL_DCS(0x16, 0x53), + PANEL_DCS(0x17, 0x55), + PANEL_DCS(0x18, 0x55), + PANEL_DCS(0x19, 0x51), + PANEL_DCS(0x1A, 0x77), + PANEL_DCS(0x1B, 0x57), + PANEL_DCS(0x1C, 0x55), + PANEL_DCS(0x1D, 0x4F), + PANEL_DCS(0x1E, 0x4D), + PANEL_DCS(0x1F, 0x5F), + PANEL_DCS(0x20, 0x4B), + PANEL_DCS(0x21, 0x49), + PANEL_DCS(0x22, 0x55), + PANEL_DCS(0x23, 0x47), + PANEL_DCS(0x24, 0x45), + PANEL_DCS(0x25, 0x41), + PANEL_DCS(0x26, 0x55), + PANEL_DCS(0x27, 0x55), + PANEL_DCS(0x28, 0x55), + PANEL_DCS(0x29, 0x55), + PANEL_DCS(0x2A, 0x55), + PANEL_DCS(0x2B, 0x55), + PANEL_DCS(0x2C, 0x13), + PANEL_DCS(0x2D, 0x15), + PANEL_DCS(0x2E, 0x15), + PANEL_DCS(0x2F, 0x01), + PANEL_DCS(0x30, 0x37), + PANEL_DCS(0x31, 0x17), + PANEL_DCS(0x32, 0x15), + PANEL_DCS(0x33, 0x0D), + PANEL_DCS(0x34, 0x0F), + PANEL_DCS(0x35, 0x15), + PANEL_DCS(0x36, 0x05), + PANEL_DCS(0x37, 0x07), + PANEL_DCS(0x38, 0x15), + PANEL_DCS(0x39, 0x09), + PANEL_DCS(0x3A, 0x0B), + PANEL_DCS(0x3B, 0x11), + PANEL_DCS(0x3C, 0x15), + PANEL_DCS(0x3D, 0x15), + PANEL_DCS(0x3E, 0x15), + PANEL_DCS(0x3F, 0x15), + PANEL_DCS(0x40, 0x15), + PANEL_DCS(0x41, 0x15), + PANEL_DCS(0x42, 0x12), + PANEL_DCS(0x43, 0x15), + PANEL_DCS(0x44, 0x15), + PANEL_DCS(0x45, 0x00), + PANEL_DCS(0x46, 0x37), + PANEL_DCS(0x47, 0x17), + PANEL_DCS(0x48, 0x15), + PANEL_DCS(0x49, 0x0C), + PANEL_DCS(0x4A, 0x0E), + PANEL_DCS(0x4B, 0x15), + PANEL_DCS(0x4C, 0x04), + PANEL_DCS(0x4D, 0x06), + PANEL_DCS(0x4E, 0x15), + PANEL_DCS(0x4F, 0x08), + PANEL_DCS(0x50, 0x0A), + PANEL_DCS(0x51, 0x10), + PANEL_DCS(0x52, 0x15), + PANEL_DCS(0x53, 0x15), + PANEL_DCS(0x54, 0x15), + PANEL_DCS(0x55, 0x15), + PANEL_DCS(0x56, 0x15), + PANEL_DCS(0x57, 0x15), + PANEL_DCS(0x58, 0x40), + PANEL_DCS(0x5B, 0x10), + PANEL_DCS(0x5C, 0x06), + PANEL_DCS(0x5D, 0x40), + PANEL_DCS(0x5E, 0x00), + PANEL_DCS(0x5F, 0x00), + PANEL_DCS(0x60, 0x40), + PANEL_DCS(0x61, 0x03), + PANEL_DCS(0x62, 0x04), + PANEL_DCS(0x63, 0x6C), + PANEL_DCS(0x64, 0x6C), + PANEL_DCS(0x65, 0x75), + PANEL_DCS(0x66, 0x08), + PANEL_DCS(0x67, 0xB4), + PANEL_DCS(0x68, 0x08), + PANEL_DCS(0x69, 0x6C), + PANEL_DCS(0x6A, 0x6C), + PANEL_DCS(0x6B, 0x0C), + PANEL_DCS(0x6D, 0x00), + PANEL_DCS(0x6E, 0x00), + PANEL_DCS(0x6F, 0x88), + PANEL_DCS(0x75, 0xBB), + PANEL_DCS(0x76, 0x00), + PANEL_DCS(0x77, 0x05), + PANEL_DCS(0x78, 0x2A), + PANEL_DCS(0xE0, 0x04), + PANEL_DCS(0x02, 0x23), + PANEL_DCS(0x09, 0x11), + PANEL_DCS(0x0E, 0x48), + PANEL_DCS(0x36, 0x49), + PANEL_DCS(0x2B, 0x08), + PANEL_DCS(0x2E, 0x03), + PANEL_DCS(0xE0, 0x00), + PANEL_DCS(0xE6, 0x02), + PANEL_DCS(0xE7, 0x06), + PANEL_DCS(0x11, 0x00), + PANEL_DELAY(120), + PANEL_DCS(0x29, 0x00), + PANEL_DELAY(50), + }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/83220?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60858109e4b07f720461e320212d7b197ec1130c Gerrit-Change-Number: 83220 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb: source site-local mainboard Kconfig.name and Kconfig files
by Jonathon Hall (Code Review) 01 Jul '24

01 Jul '24

Attention is currently required from: Alexander Couzens, Angel Pons, David Hendricks, Evgeny Zinoviev, Felix Held, Felix Singer, Jeremy Soller, Martin L Roth, Matt DeVillier, Michael Niewöhner, Michał Żygowski, Philipp Hug, Piotr Król, Ron Minnich, Sean Rhodes, Tim Crawford. Jonathon Hall has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/83119?usp=email ) Change subject: mb: source site-local mainboard Kconfig.name and Kconfig files ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Yeah. […] @foss@mniewoehner.de - you can extend a choice from another Kconfig if the choice is named, like `choice MAINBOARD_MODEL_<vendor>` (mentioned this in another comment too - https://review.coreboot.org/c/coreboot/+/83119/comments/52813f26_fffaa591). Still requires modifying the in-tree Kconfigs though since they don't have names right now. -- To view, visit https://review.coreboot.org/c/coreboot/+/83119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4106fea7197c979e6648ebbbbaa107070c916727 Gerrit-Change-Number: 83119 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Jul 2024 13:35:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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