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Change subject: 3rdparty/fsp: Update submodule to upstream master
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
......................................................................
Patch Set 23: Code-Review+2
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Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#23).
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
......................................................................
soc/intel/xeon_sp/gnr: Add soc_pci_domain_fill_ssdt
Domain device objects are created with HID/CID/UID/_OSC/_PXM
Dynamic domain SSDT generation could benefit the support of SoCs with
multiple SKUs, or the case where one set of codes supports multiple
SoCs. One possible side-effect might be the extra performance cost for
generating these tables, which should not bring big impact on high
performance server CPUs.
GNR codes run with dynamic domain SSDT generation to fit for both
GraniteRapids and SierraForest SoCs.
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB
Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/mainboard/intel/avenuecity_crb/dsdt.asl
M src/mainboard/intel/beechnutcity_crb/dsdt.asl
M src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/acpi/uncore.asl
M src/soc/intel/xeon_sp/gnr/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
6 files changed, 72 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81374/23
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Change subject: 3rdparty/fsp: Update submodule to upstream master
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Patch Set 3: Code-Review+2
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Patch Set 4: Code-Review+2
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Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71 TEST=Validated on qualcomm sc7180 development board
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
please review
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Change subject: tree: Use <console/console.h> only when used
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/xeon_sp/gnr: Support fast boot
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Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
......................................................................
Patch Set 38:
(1 comment)
Patchset:
PS38:
> What's an OS key? The one they call a "software key"? So just always using `sw_key_p. […]
Sorry, yes, I meant SW key. I've built the image after basically repeating
https://github.com/open-power/sb-signing-utils/blob/master/sign-with-local-…
with `hw_key_a.key` changed to `sw_key_p.key` (no idea why it uses HW when
SW is also in that repo) and it looks correct, i.e. all signatures and keys
are in place, but obviously hash and signatures are different than in original
HBB. I'll try updating and booting later today to see if this is enough.
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