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Change subject: chromeec: supporting reading long battery strings
......................................................................
Patch Set 3:
(1 comment)
File src/ec/google/chromeec/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/82775/comment/18f5ec56_239eb3a7?us… :
PS2, Line 61: string index
> Added some additional information, including the symbolic names used in the EC.
thanks
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Change subject: chromeec: supporting reading long battery strings
......................................................................
Patch Set 3: Code-Review+2
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Change subject: chromeec: supporting reading long battery strings
......................................................................
Patch Set 3:
(1 comment)
File src/ec/google/chromeec/acpi/battery.asl:
https://review.coreboot.org/c/coreboot/+/82775/comment/e8e66d3f_4220a71d?us… :
PS2, Line 61: string index
> nit: if you could highlight in the comment section the meaning of index 1-3
Added some additional information, including the symbolic names used in the EC.
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Hello Caveh Jalali, Forest Mittelberg, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82775?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: chromeec: supporting reading long battery strings
......................................................................
chromeec: supporting reading long battery strings
The Chrome EC currently supports two ways to read battery strings on
ACPI platforms:
* Read up to 8 bytes from EC shared memory BMFG, BMOD, ...
* Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from
the response. This is assumed to be exclusively controlled by the OS,
because host commands' use of buffers is prone to race conditions.
To support readout of longer strings via ACPI mechanisms, this change
adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473)
and allows ACPI firmware to read strings of arbitrary length (currently
limited to 64 characters in the implementation) from the EC and to
determine whether this function is supported by the EC (falling back to
shared memory if not).
BUG=b:339171261
TEST=on yaviks, the EC console logs FIFO readout messages when used in
ACPI and correct strings are shown in the OS. If EC support is
removed, correct strings are still shown in the OS.
BRANCH=nissa
Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M src/ec/google/chromeec/acpi/battery.asl
M src/ec/google/chromeec/acpi/ec.asl
2 files changed, 92 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/82775/3
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Change subject: mb/google/brox/var/lotso: Tune I2C frequency for 400 kHz
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83290/comment/b2d90afd_5d057bf8?us… :
PS5, Line 7: for 400 kHz
> Yes, it is not strictly equal to 400khz, but it is close to 400khz. This is also reasonable.
Done
https://review.coreboot.org/c/coreboot/+/83290/comment/44b2e48c_10e149b6?us… :
PS5, Line 17: HW: Change R8409/R8411 to 33ohm.
> Since the hardware design affects the I2C frequency, some hardware settings also need to be adjusted […]
Done
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Change subject: mb/google/brox/var/lotso: Tune I2C frequency for 400 kHz
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83290/comment/4e4eaa77_e62b81aa?us… :
PS5, Line 7: for 400 kHz
> Looking at the numbers, than this should be: … to be less than 400 kHz?
Yes, it is not strictly equal to 400khz, but it is close to 400khz. This is also reasonable.
https://review.coreboot.org/c/coreboot/+/83290/comment/91097cfd_f9482e4e?us… :
PS5, Line 17: HW: Change R8409/R8411 to 33ohm.
> Sorry, I do not understand this comment. […]
Since the hardware design affects the I2C frequency, some hardware settings also need to be adjusted, so here are some resistor value adjustments.
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Change subject: soc/intel/common: Skip ME version log for Lite SKU
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Patch Set 2: Code-Review+2
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Change subject: mb/google/rex: Set cnvi_wifi bluetooth companion device
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS3:
you may need to do the same for Intel MTLRVPs?
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Change subject: soc/intel/cmn/cse: Make ME firmware version query function static
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/cmn/cse: Conditionally disable ME status reporting
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Patch Set 3: Code-Review+2
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