coreboot-gerrit July 2024

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[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Felix Singer (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Jan Philipp Groß, Máté Kukri. Felix Singer has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82760?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... Patch Set 15: Code-Review+2 (3 comments) Patchset: PS15: Just a few nits. Otherwise looks good to me! File src/mainboard/asrock/z97e-itx_ac/Kconfig: https://review.coreboot.org/c/coreboot/+/82760/comment/f05b97da_ea748228?us… : PS15, Line 1: ## SPDX-License-Identifier: GPL-2.0-or-later Add blank line here. File src/mainboard/asrock/z97e-itx_ac/dsdt.asl: https://review.coreboot.org/c/coreboot/+/82760/comment/8cd95ca6_5afb633c?us… : PS15, Line 18: /* global NVS and variables. */ Seems superfluous. Please remove. -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 15 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Jul 2024 15:12:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Angel Pons (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Jan Philipp Groß, Máté Kukri. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82760?usp=email ) Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... Patch Set 15: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 15 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Jul 2024 15:12:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Z87M OC Formula (Haswell)
by Felix Singer (Code Review) 02 Jul '24

02 Jul '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82906?usp=email ) Change subject: mb/asrock: Add Z87M OC Formula (Haswell) ...................................................................... mb/asrock: Add Z87M OC Formula (Haswell) This port was done via autoport and subsequent manual tweaking. Special thanks to Nicholas Chin! This port would have never succeeded without his help. The board features two socketed DIP-8 SPI flash chips, as well as a BIOS selection switch and onboard Power and Reset switches. Working: - Haswell MRC.bin - All four DDR3/DDR3L DIMM slots - S3 suspend and resume - Libgfxinit - HDMI-Out Port - USB 2.0 Ports - Vertical Type A USB 2.0 - USB 3.1 Gen1 Ports - HD Audio Jack (audio output) - Front panel audio connector (audio output) - RJ-45 Gigabit LAN Port - SATA3 6.0 Gb/s connectors - mSATA/mini-PCI Express slot - half mini-PCI Express slot - PCI Express 3.0 x16 slots (both) - PCI Express 2.0 x4 slot - PCI Express 2.0 x1 slot Working (board-specific) - Power Switch with LED (functional, yet no LED) - Reset Switch with LED (functional, yet no LED) - BIOS Selection Switch - Slow Mode Switch (locks the CPU at 800MHz) not (yet) tested: - IR header - COM Port header - Power LED header - eSATA connector - USB 2.0 headers - PS/2 Mouse/Keyboard Port - HDMI-In Port - Optical SPDIF Out Port not (yet) working: - Software fan control: While the Nuvoton chip is correctly discovered, the numbering of the fan connectors is faulty, resulting in the wrong fan being controlled. - Dr. Debug: on vendor firmware, the LEDs turn off after successful boot. On coreboot, the LED shows two bright zeros after boot. - Post Status Checker (PSC) Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- A src/mainboard/asrock/z87m_oc_formula/Kconfig A src/mainboard/asrock/z87m_oc_formula/Kconfig.name A src/mainboard/asrock/z87m_oc_formula/Makefile.mk A src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl A src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl A src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl A src/mainboard/asrock/z87m_oc_formula/board_info.txt A src/mainboard/asrock/z87m_oc_formula/bootblock.c A src/mainboard/asrock/z87m_oc_formula/data.vbt A src/mainboard/asrock/z87m_oc_formula/devicetree.cb A src/mainboard/asrock/z87m_oc_formula/dsdt.asl A src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads A src/mainboard/asrock/z87m_oc_formula/gpio.c A src/mainboard/asrock/z87m_oc_formula/hda_verb.c A src/mainboard/asrock/z87m_oc_formula/romstage.c 15 files changed, 510 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig b/src/mainboard/asrock/z87m_oc_formula/Kconfig new file mode 100644 index 0000000..c05f2fd --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87M_OC_FORMULA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87m_oc_formula" + +config MAINBOARD_PART_NUMBER + default "Z87M OC Formula" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top-most of the two USB-3.0-Ports beneath the RJ45 jack. +endif diff --git a/src/mainboard/asrock/z87m_oc_formula/Kconfig.name b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name new file mode 100644 index 0000000..0412b1c0 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87M_OC_FORMULA + bool "Z87M OC Formula" diff --git a/src/mainboard/asrock/z87m_oc_formula/Makefile.mk b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk new file mode 100644 index 0000000..93f729d --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/Makefile.mk @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87m_oc_formula/board_info.txt b/src/mainboard/asrock/z87m_oc_formula/board_info.txt new file mode 100644 index 0000000..072d258 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z87M%20OC%20Formula/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 (2x) +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87m_oc_formula/bootblock.c b/src/mainboard/asrock/z87m_oc_formula/bootblock.c new file mode 100644 index 0000000..1cec5c4 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/asrock/z87m_oc_formula/data.vbt b/src/mainboard/asrock/z87m_oc_formula/data.vbt new file mode 100644 index 0000000..0f70e00 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87m_oc_formula/devicetree.cb b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb new file mode 100644 index 0000000..cbde4cb --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/devicetree.cb @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "gpu_dp_c_hotplug" = "4" + + chip cpu/intel/haswell + device cpu_cluster 0 on + ops haswell_cpu_bus_ops + end + end + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PEG + end + device pci 02.0 on # iGPU + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x2246" + register "sata_port0_gen3_dtle" = "0xa" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # MEI #1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # MEI #2 + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1151 + end + device pci 1c.0 on # RP #1 + subsystemid 0x1849 0x8c10 + end + device pci 1c.1 on # RP #2 mPCIe slot + subsystemid 0x1849 0x8c12 + end + device pci 1c.2 on # RP #3 + end + device pci 1c.3 on # RP #4 PCIe NVMe Controller + end + device pci 1c.4 on # RP #5 + end + device pci 1c.5 on # RP #6 + end + device pci 1c.6 on # RP #7 + end + device pci 1c.7 on # RP #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on # GPIO0 + irq 0xe0 = 0xf9 # + GPIO0 direction + irq 0xe1 = 0xfd # + GPIO0 value + end + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on # GPIO1 + irq 0xf0 = 0xf1 # + GPIO1 direction + irq 0xf1 = 0xf1 # + GPIO1 value + end + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on # GPIO7 + irq 0xe0 = 0xff # + GPIO7 direction + end + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # + Power RAM in S3 + irq 0xf0 = 0x20 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87m_oc_formula/dsdt.asl b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl new file mode 100644 index 0000000..2eb0805 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads new file mode 100644 index 0000000..61dc90a --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI2, -- DP + HDMI3, -- HDMI + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87m_oc_formula/gpio.c b/src/mainboard/asrock/z87m_oc_formula/gpio.c new file mode 100644 index 0000000..01d39f2 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/gpio.c @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87m_oc_formula/hda_verb.c b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c new file mode 100644 index 0000000..ab7da86 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87m_oc_formula/romstage.c b/src/mainboard/asrock/z87m_oc_formula/romstage.c new file mode 100644 index 0000000..44932e7 --- /dev/null +++ b/src/mainboard/asrock/z87m_oc_formula/romstage.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/82906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Gerrit-Change-Number: 82906 Gerrit-PatchSet: 13 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: mb/asrock: Add Z87M OC Formula (Haswell)
by Felix Singer (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Angel Pons, Jan Philipp Groß, Máté Kukri. Felix Singer has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82906?usp=email ) Change subject: mb/asrock: Add Z87M OC Formula (Haswell) ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82906?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746 Gerrit-Change-Number: 82906 Gerrit-PatchSet: 12 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jul 2024 15:09:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/asrock: Add Fatal1ty Z87 Professional (Haswell)
by Angel Pons (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Felix Singer, Jan Philipp Groß, Máté Kukri, Paul Menzel. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82913?usp=email ) Change subject: mb/asrock: Add Fatal1ty Z87 Professional (Haswell) ...................................................................... Patch Set 9: Code-Review+2 (4 comments) File src/mainboard/asrock/fatal1ty_z87_professional/Kconfig: https://review.coreboot.org/c/coreboot/+/82913/comment/8c4675b0_954d4fc3?us… : PS9, Line 1: ## SPDX-License-Identifier: GPL-2.0-only Add newline File src/mainboard/asrock/fatal1ty_z87_professional/bootblock.c: https://review.coreboot.org/c/coreboot/+/82913/comment/d8badf5b_846a27e4?us… : PS9, Line 7: { I never got around to look into this File src/mainboard/asrock/fatal1ty_z87_professional/dsdt.asl: https://review.coreboot.org/c/coreboot/+/82913/comment/bdca3f4e_b20f6c96?us… : PS9, Line 3: Drop newline File src/mainboard/asrock/fatal1ty_z87_professional/hda_verb.c: https://review.coreboot.org/c/coreboot/+/82913/comment/69f913f4_2de60790?us… : PS9, Line 20: Drop newline -- To view, visit https://review.coreboot.org/c/coreboot/+/82913?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266 Gerrit-Change-Number: 82913 Gerrit-PatchSet: 9 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Jul 2024 15:08:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: 3rdparty/vboot: Update submodule to upstream main
by Felix Singer (Code Review) 02 Jul '24

02 Jul '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83295?usp=email ) Change subject: 3rdparty/vboot: Update submodule to upstream main ...................................................................... 3rdparty/vboot: Update submodule to upstream main Updating from commit id 09fcd218: 2024-02-23 06:42:12 +0000 - (Makefile: Test compiler for -Wincompatible-function-pointer-types) to commit id b6f44e62: 2024-07-01 04:30:14 +0000 - (futility: updater: Increase try count from 8 to 10) This brings in 58 new commits: b6f44e62 futility: updater: Increase try count from 8 to 10 cfc87db2 OWNERS: Add czapiga eabf5784 OWNERS: Remove twawrzynczak and quasisec f8af818e host: Add stub implementation for pkcs11 key aaf4ecbb crossystem: Add support for Panther Lake gpiochip de89c5cd make_dev_ssd: allow ptracers to write proc/mem ffc9cc15 utility: Add vbnv_util.py for debugging b6174bdb futility: show: Print keyblock signature size and data size 6e39c99f Android: Add support for doing zipalign before doing apksigner ead73381 futility: flash: Enhance WP status reporting by adding more instructions c3368084 futility: modify private key validation to work for both local and cloud c22d72f8 futility: flash: Correct the output syntax of 32bit hex f423ae13 crossystem: Drop support for tried_fwb and fwb_tries fc5488c7 futility: flash: Correct the allowlist of options 16dede85 Revert "futility: Split load_firmware_image() into two functions for AP and EC" ded07831 futility: Try to load ecrw versions regardless of image type 7a685705 futility: Refactor code for --manifest f5ad0856 futility: Add more checks for incompatible arguments 05659d33 futility/updater_manifest: Warn about inconsistent RW versions 6720827b futility: Support ecrw version for --manifest daae7e56 futility: Split load_firmware_image() into two functions for AP and EC 40c77bba futility: Warn about inconsistent RW_FWID_A and RW_FWID_B versions c168ac8e tests/futility/data: Update bios_geralt_cbfs.bin with swapped ecrw 512648ae host/lib: Add cbfstool_file_exists() and cbfstool_extract() e37e6511 sign_official_build: add missing info keyword 2c0758b4 sign_official_build: loem support for firmware 016f6149 scripts/image_signing/swap_ec_rw: Always add ecrw.* as raw CBFS file b26c700a scripts/image_signing/swap_ecrw: Support ecrw.version 2e8d1003 tlcl: Add const qualifier to TlclTakeOwnership arguments 96b8674c host: stop installing unused image signing scripts 8da83c43 Android: Handle update certs using for hardcoded certs 4ca60534 scripts/image_signing: Add swap_ec_rw d30d6b54 make_dev_ssd: Remove logic choosing editor value 4cc5d090 futility/dump_fmap: Fix error message prefix for '-x' e7062a58 futility/dump_fmap: Exit with error if specified section is not found 4489dd09 scripts: Remove newbitmaps directory 8dcc82b0 host/lib/cbfstool: Redesign cbfstool_get_config_value() API 856fd693 Android: Hack for now to let things silently fail instead of erroring 28845c97 sign_uefi: Handle case where the crdyshim key does not exist 201244c3 sign_uefi_unittest: Refactor in preparation for more tests 702f8b53 tests: Add tests for cbfstool_get_config_value() 52a21327 Android: Add support for gcloud KMS in android signing 3310c49f tests/futility/test_update.sh: Use unique test names for IFD tests 493f7afc sign_gsc_firmware: add support for Nightly target 5c307cad keycfg: more consistent typo fix 11e4f60b image_signing: Add missing arg in sign_uefi_kernel 37c730d8 keycfg: handle arrays appropriately in key_config 59c37697 sign_uefi: Add detached crdyboot signature b66926e2 sign_uefi: Refactor the is-pkcs11 function for reuse 94aa8b80 image_signing: Pass crdyshim private key to sign_uefi.py 0ac99bcb sign_uefi: Stop signing crdyboot files with sbsign 6f6a6432 vboot_reference-sys: replace denylist with allowlist 73ebd8f8 vboot_reference-sys: add vboot_host pkg-config fallback 476282ef make_dev_ssd: Skip firmware validity checks on nonchrome 9330a65a vboot_reference: Add support for allowing overlayfs 48c8833f sign_official_build: remove cloud-signing aa70bb19 create_new_keys.sh: add --arv-root-uri 38d1af69 sign_official_build: Dedup calls to sign_uefi.py Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83295 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index 09fcd21..b6f44e6 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 09fcd2184f9c714829503e84b8a7dfe7f2584e00 +Subproject commit b6f44e62650e563cca651bd4349c418450dd1bd3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83295?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14aaf1e1e230107e7bae60195c7e4684bf5a0533 Gerrit-Change-Number: 83295 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 02 Jul '24

02 Jul '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83294?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... 3rdparty/fsp: Update submodule to upstream master The filename of the Elkhart Lake FSP binary changed in the FSP repository. It's unlikely that it will be renamed to the original name soon. Thus, update the filename in the coreboot repository. Updating from commit id cc6399e: 2024-03-04 15:40:41 +0800 - (IoT MTL-UH & MTL-PS PV (3471_49) FSP) to commit id 800c857: 2024-06-25 15:47:28 +0800 - (Update Fsp.fd) This brings in 23 new commits: 800c857 Update Fsp.fd 41e4590 NEX AZB IPU24.4 (5254_00) FSP 0efd8a3 IoT RPL-PS PV (5045_47) FSP 196e3fe Update README.md 380afd8 Update README.md 5dc88ca NEX ADL-PS IPU24.3/MR6 (5045_02) FSP 22762e9 Merge branch 'master' of https://github.com/intel/FSP 8134dbd Elkhart Lake IPU2024.3 FSP 3819544 add required SECURITY.md file for OSSF Scorecard compliance a6ee963 Delete AlderLakeFspBinPkg.dec 9d819ea Deprecate Client/AlderLakeFspBinPkg f963690 Raptor Lake FSP C.1.C8.50 f67f9ef Raptor Lake FSP C.0.C8.50 68c3cfa NEX ADL-PS IPU 2024.3 (5045_02) FSP f0d04d9 NEX ADL-P IPU 2024.3 (5045_02) FSP 6fa139c NEX ADL-S IPU 2024.3 (5045_02) FSP c4af5ac NEX TGL IPU 2024.3 (7092_01) FSP 8cf0372 IoT ADL-N MR4 (5061_00) e5ceb0b Merge branch 'master' of https://github.com/intel/FSP aada6a5 Elkhart Lake IPU2024.2 FSP 90d1d3b Update README.md 1a5a3ee Testing 61c069a NEX RPL-S MR3 (4445_03) FSP Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83294 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/fsp M src/soc/intel/elkhartlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/3rdparty/fsp b/3rdparty/fsp index cc6399e..800c857 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit cc6399e8c759ad4ed83c2d6ea568fd918fc9bc06 +Subproject commit 800c85770b458ee7f7eeb1276b46e904590d3bd7 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 9bee9be..58c4556 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -192,7 +192,7 @@ config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSP.fd" + default "3rdparty/fsp/ElkhartLakeFspBinPkg/FspBin/FSPRel.bin" config PSE_ENABLE bool "Enable PSE ARM controller" -- To view, visit https://review.coreboot.org/c/coreboot/+/83294?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47013bce65054f2c496c9aa7c16e55b51d65e5fe Gerrit-Change-Number: 83294 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
by Krystian Hebel (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Arthur Heymans, Elyes Haouas, Sergii Dmytruk. Krystian Hebel has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/coreboot/+/67065?usp=email ) Change subject: 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER ...................................................................... Patch Set 38: -Code-Review (1 comment) Patchset: PS38: > Sorry, yes, I meant SW key. I've built the image after basically repeating […] Unfortunately, this is not enough, booting fails early with very little useful information. I presume this is a checkstop caused by lack of SecureROM (12K block of code with SHA and other verification functions) at the end of HBBL partition, which in case of coreboot is bootblock. We can't just append it because bootblock is slightly too big currently, we would have to get rid of printing or enable LTO to make it fit. It does boot when secure boot is disabled by a jumper, to some point (coreboot complains about MEMD format in 2.10, perhaps it has changed, but this isn't related to secure boot). Fully enabling secure boot doesn't seem to be trivial and will most likely need follow-up patches. Still, since the container is required even with secure boot disabled, it makes sense to creating those signatures as they should be created, with all signatures filled in. We can worry about the rest later, but the fact that this isn't complete solution deserves mentioning at least in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/67065?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d Gerrit-Change-Number: 67065 Gerrit-PatchSet: 38 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Georgi Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 02 Jul 2024 14:55:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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[M] Change in coreboot[main]: util/ifdtool: fix spacing issues
by Felix Held (Code Review) 02 Jul '24

02 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83281?usp=email ) Change subject: util/ifdtool: fix spacing issues ...................................................................... util/ifdtool: fix spacing issues Ensure consistent spacing around colons in bit fields, operators, statements and function calls. Found by the linter (check-style). Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83281 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M util/ifdtool/ifdtool.c 1 file changed, 30 insertions(+), 31 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 1c3e810..033ccf4 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -51,20 +51,20 @@ * protected region start address, where bit 0-11 of * the start address are assumed to be zero. */ - uint32_t start:15; + uint32_t start : 15; /* Specifies read protection is enabled */ - uint32_t read_protect_en:1; + uint32_t read_protect_en : 1; /* * End Address: bit 16-30 of the GPRD represents the * protected region end address, where bit 0-11 of * the end address are assumed to be 0xfff. */ - uint32_t end:15; + uint32_t end : 15; /* Specifies write protection is enabled */ - uint32_t write_protect_en:1; + uint32_t write_protect_en : 1; } __packed data; uint32_t value; @@ -133,9 +133,9 @@ /* Scan for FD signature */ for (i = 0; i < (size - 4); i += 4) { - if (*(uint32_t *) (image + i) == 0x0FF0A55A) { + if (*(uint32_t *)(image + i) == 0x0FF0A55A) { found = 1; - break; // signature found. + break; // signature found. } } @@ -144,7 +144,7 @@ return NULL; } - struct fdbar *fdb = (struct fdbar *) (image + i); + struct fdbar *fdb = (struct fdbar *)(image + i); return PTR_IN_RANGE(fdb, image, size) ? fdb : NULL; } @@ -168,9 +168,8 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fcba *fcba = (struct fcba *) (image + ((fdb->flmap0 & 0xff) << 4)); + struct fcba *fcba = (struct fcba *)(image + ((fdb->flmap0 & 0xff) << 4)); return PTR_IN_RANGE(fcba, image, size) ? fcba : NULL; - } static struct fmba *find_fmba(char *image, int size) @@ -178,7 +177,7 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmba *fmba = (struct fmba *) (image + ((fdb->flmap1 & 0xff) << 4)); + struct fmba *fmba = (struct fmba *)(image + ((fdb->flmap1 & 0xff) << 4)); return PTR_IN_RANGE(fmba, image, size) ? fmba : NULL; } @@ -211,7 +210,7 @@ struct fdbar *fdb = find_fd(image, size); if (!fdb) return NULL; - struct fmsba *fmsba = (struct fmsba *) (image + ((fdb->flmap2 & 0xff) << 4)); + struct fmsba *fmsba = (struct fmsba *)(image + ((fdb->flmap2 & 0xff) << 4)); return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL; } @@ -355,7 +354,7 @@ if (region_type >= max_regions) { fprintf(stderr, "Invalid region type %d.\n", region_type); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } flreg = frba->flreg[region_type]; @@ -387,7 +386,7 @@ { if (region_type >= max_regions) { fprintf(stderr, "Invalid region type.\n"); - exit (EXIT_FAILURE); + exit(EXIT_FAILURE); } return region_names[region_type].pretty; @@ -452,7 +451,7 @@ * 4 bytes of space. */ if (sorted[i] == frba) - return MIN((sorted[i+1] - sorted[i])/4, MAX_REGIONS); + return MIN((sorted[i + 1] - sorted[i]) / 4, MAX_REGIONS); } /* Never reaches this point */ return 0; @@ -717,7 +716,7 @@ printf("\nFound Component Section\n"); printf("FLCOMP 0x%08x\n", fcba->flcomp); printf(" Dual Output Fast Read Support: %ssupported\n", - (fcba->flcomp & (1 << 30))?"":"not "); + (fcba->flcomp & (1 << 30)) ? "" : "not "); printf(" Read ID/Read Status Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 27) & 7); printf("\n Write/Erase Clock Frequency: "); @@ -725,7 +724,7 @@ printf("\n Fast Read Clock Frequency: "); decode_spi_frequency((fcba->flcomp >> 21) & 7); printf("\n Fast Read Support: %ssupported", - (fcba->flcomp & (1 << 20))?"":"not "); + (fcba->flcomp & (1 << 20)) ? "" : "not "); if (is_platform_with_100x_series_pch() && chipset != CHIPSET_100_200_SERIES_SUNRISE_POINT) { printf("\n Read eSPI/EC Bus Frequency: "); @@ -977,7 +976,7 @@ static void dump_vtba(const struct vtba *vtba, int vtl) { int i; - int max_len = sizeof(struct vtba)/sizeof(struct vscc); + int max_len = sizeof(struct vtba) / sizeof(struct vscc); int num = (vtl >> 1) < max_len ? (vtl >> 1) : max_len; printf("ME VSCC table:\n"); @@ -997,10 +996,10 @@ for (i = 0; i < 4; i++) { printf("%02x:", i << 4); for (j = 0; j < 16; j++) - printf(" %02x", oem[(i<<4)+j]); - printf ("\n"); + printf(" %02x", oem[(i << 4) + j]); + printf("\n"); } - printf ("\n"); + printf("\n"); } static void dump_fd(char *image, int size) @@ -1124,11 +1123,11 @@ sorted_regions[count_regions] = region; // basically insertion sort - for (int i = count_regions-1; i >= 0 ; i--) { - if (sorted_regions[i].base > sorted_regions[i+1].base) { + for (int i = count_regions - 1; i >= 0; i--) { + if (sorted_regions[i].base > sorted_regions[i + 1].base) { struct region tmp = sorted_regions[i]; - sorted_regions[i] = sorted_regions[i+1]; - sorted_regions[i+1] = tmp; + sorted_regions[i] = sorted_regions[i + 1]; + sorted_regions[i + 1] = tmp; } } count_regions++; @@ -1858,8 +1857,8 @@ { if (ifd_version >= IFD_VERSION_2) { printf("%sting the HAP bit to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[0] |= (1 << 16); else @@ -1868,8 +1867,8 @@ if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("%sting the ICH_MeDisable, MCH_MeDisable, " "and MCH_AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) { /* MCH_MeDisable */ fmsba->data[0] |= 1; @@ -1884,8 +1883,8 @@ } } else { printf("%sting the AltMeDisable to %s Intel ME...\n", - altmedisable?"Set":"Unset", - altmedisable?"disable":"enable"); + altmedisable ? "Set" : "Unset", + altmedisable ? "disable" : "enable"); if (altmedisable) fpsba->pchstrp[10] |= (1 << 7); else @@ -2570,7 +2569,7 @@ // generate new filename if (new_filename == NULL) { - new_filename = (char *) malloc((strlen(filename) + 5) * sizeof(char)); + new_filename = (char *)malloc((strlen(filename) + 5) * sizeof(char)); if (!new_filename) { printf("Out of memory.\n"); exit(EXIT_FAILURE); -- To view, visit https://review.coreboot.org/c/coreboot/+/83281?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I817b1dcf106cc360a7db56e5b4b0716d5419e2cd Gerrit-Change-Number: 83281 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: Makefile.mk: Move recently introduced warning options to xcompile
by Elyes Haouas (Code Review) 02 Jul '24

02 Jul '24

Attention is currently required from: Felix Singer, Martin L Roth. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83306?usp=email ) Change subject: Makefile.mk: Move recently introduced warning options to xcompile ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibadcd22f99703ced700a1b671e7696255ecf9e71 Gerrit-Change-Number: 83306 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jul 2024 13:40:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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