Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83432?usp=email )
Change subject: soc/intel/alderlake: Fix system hang by enabling SMI handling
......................................................................
soc/intel/alderlake: Fix system hang by enabling SMI handling
Issue: System hang occurred due to unhandled SPI synchronous SMI,
triggered by LOCK_ENABLE bit and WPD assertion.
Solution: Enabled SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE configuration
to allow the system to handle and clear SPI synchronous SMI.
BUG=b:350623902
TEST=reboot test on 40 google/xol by ODM, all passed w/o
hang.
Change-Id: I4c14b1e3d537e46e671e950c91c9d0042fe26836
Signed-off-by: Jamie Chen <jamie.chen(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/83432/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 9b6e161..470dbf4 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -76,6 +76,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
select SOC_INTEL_COMMON_BLOCK_VTD
select SOC_INTEL_COMMON_BLOCK_XHCI
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Gerrit-Change-Number: 83432
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Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/82174?usp=email )
Change subject: soc/intel/meteorlake: Enable SOC config override during boot
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/82174/comment/8ca62d52_e39343f2?us… :
PS4, Line 785: const struct soc_intel_meteorlake_config *config)
> I failed to understand how this change relates to the commit message.
Per discussion with Will (WonkyuKim), one of changes is to move the function that provides read-write/modified config out of soc_silicon_init_params().The purpose of this is to make soc_silicon_init_params() function only for init. Removing 'const' from the soc_silicon_init_params() function indicates that this function will not make changes to 'config'. Now, the flow to modify config are the same between romstage & ramstage.
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Hello Anil Kumar K, Bora Guvendik, Jamie Ryu, Martin L Roth, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83225?usp=email
to look at the new patch set (#3).
Change subject: payloads/depthcharge: support depthcharge build with local changes
......................................................................
payloads/depthcharge: support depthcharge build with local changes
Allow building with local changes.
Add dependency and target for generated static_fw_config.h.
This ensures this file is generated prior to building depthcharge.
Fix 'git fetch' for the repo other than origin/main. It only fetches
latest code if the branch name is origin/main. Use $(DEPTHCHARGE_BRANCH)
to fetch when different branch is used.
TEST=depthcharge should build with local changes
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I95c1f71ae149537a2191734a62f416b7b6f41fc6
---
M Makefile.mk
M payloads/external/Makefile.mk
M payloads/external/depthcharge/Makefile
3 files changed, 15 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/83225/3
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Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83225?usp=email )
Change subject: payloads/depthcharge: support depthcharge build with local changes
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83225/comment/00af2c28_bbfa9dbf?us… :
PS1, Line 14: deptcharge
> depthcharge
Done
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Julius Werner has posted comments on this change by Ashish Kumar Mishra. ( https://review.coreboot.org/c/coreboot/+/83420?usp=email )
Change subject: vc/google/chromeos: Add configurable compression for logo file in cbfs
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
> > Is there really a platform where the most efficient compression algorithm for ramstage is LZMA but […]
Hmm... okay, so you're saying LZ4 is faster, but it doesn't fit when everything is LZ4, and so you want individual options for every file so that you can at least make as many files LZ4 as possible without overflowing? Okay, I get that, I guess. It's not pretty but I guess it's what we need.
Let's at least try to match the defaults so that everything follows the ramstage compression option by default unless explicitly overridden.
File src/vendorcode/google/chromeos/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/83420/comment/3c273dc4_544786f6?us… :
PS2, Line 29: ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZMA),y)
: cb_logo.bmp-compression := LZMA
: else ifeq ($(CONFIG_BMP_LOGO_COMPRESS_LZ4),y)
: cb_logo.bmp-compression := LZ4
: endif
:
> > BMP_LOGO_COMPRESS_FLAG := none […]
+1 to what Karthik said
I'm not sure why you need a HAVE_... option in addition to the choice itself? I think you should just need the choice. Just make the defaults match the normal ramstage defaults:
```
choice
...
default BMP_LOGO_COMPRESS_LZMA if COMPRESS_RAMSTAGE_LZMA
default BMP_LOGO_COMPRESS_LZ4 if COMPRESS_RAMSTAGE_LZ4
default BMP_LOGO_COMPRESS_NONE
```
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