Attention is currently required from: Felix Held, Fred Reitberger, Martin L Roth.
George Burgess has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email )
Change subject: amdfwtool: make fields unsigned
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Thank you all!
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Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586
Gerrit-Change-Number: 83412
Gerrit-PatchSet: 2
Gerrit-Owner: George Burgess <gbiv(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
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Gerrit-Comment-Date: Thu, 11 Jul 2024 15:37:04 +0000
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83414?usp=email )
Change subject: libpayload/x86: Add x86-64 support to rdtsc()
......................................................................
libpayload/x86: Add x86-64 support to rdtsc()
This patch adds support for x86-64 to the rdtsc() function, allowing
it to correctly read the Time Stamp Counter (TSC) on both 32-bit and
64-bit x86 architectures.
BUG=b:242829490, b:351851626
TEST=Builds and boots on google/rex0 and google/rex64 systems and
manually verified correct TSC readings on x86-32 and x86-64 hardware.
Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83414
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M payloads/libpayload/include/x86/arch/rdtsc.h
1 file changed, 3 insertions(+), 3 deletions(-)
Approvals:
Julius Werner: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/payloads/libpayload/include/x86/arch/rdtsc.h b/payloads/libpayload/include/x86/arch/rdtsc.h
index 41ab24a..2c92a9f 100644
--- a/payloads/libpayload/include/x86/arch/rdtsc.h
+++ b/payloads/libpayload/include/x86/arch/rdtsc.h
@@ -33,9 +33,9 @@
static u64 rdtsc(void)
{
- u64 val;
- __asm__ __volatile__ ("rdtsc" : "=A" (val));
- return val;
+ u32 lo, hi;
+ __asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));
+ return (u64)hi << 32 | lo;
}
#endif
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Gerrit-MessageType: merged
Gerrit-Project: coreboot
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Gerrit-Change-Id: I0afac3db2e82a245a37c2e5cf2302bf1dad62c01
Gerrit-Change-Number: 83414
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83396?usp=email )
Change subject: soc/intel/meteorlake: Conditional selection of CSE Lite PSR
......................................................................
soc/intel/meteorlake: Conditional selection of CSE Lite PSR
This patch makes the selection of `SOC_INTEL_CSE_LITE_PSR` conditional
on both `MAINBOARD_HAS_CHROMEOS` and `SOC_INTEL_CSE_LITE_SKU` being
enabled.
This ensures that CSE Lite PSR is only active when both ChromeOS is the
target platform and CSE sync is performed inside coreboot.
BUG=b:305898363
TEST=Able to build google/rex.
Change-Id: I7199c034bbe6e7f077650417da67fa544f0b49d5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83396
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, approved
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 622d35f..5ec891f 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -91,7 +91,7 @@
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_IOC
select SOC_INTEL_CRASHLOG
- select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_IOE_DIE_SUPPORT
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