coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: soc/intel: Extend CSE RW Update and ME read access for payload sync
by Subrata Banik (Code Review) 11 Jul '24

11 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83395?usp=email ) Change subject: soc/intel: Extend CSE RW Update and ME read access for payload sync ...................................................................... soc/intel: Extend CSE RW Update and ME read access for payload sync Modify the dependencies for `SOC_INTEL_CSE_RW_UPDATE` and `ME_REGION_ALLOW_CPU_READ_ACCESS` config options to include `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD`. This allows these features to be enabled even when CSE sync is performed in the payload, not just within coreboot (when `SOC_INTEL_CSE_LITE_SKU` config is enabled). BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83395 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/common/block/cse/Kconfig M src/southbridge/intel/common/firmware/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index d8d2456..c4aa6b5 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -184,7 +184,7 @@ config SOC_INTEL_CSE_RW_UPDATE bool "Enable the CSE RW Update Feature" default n - depends on SOC_INTEL_CSE_LITE_SKU + depends on SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD help This config will enable CSE RW firmware update feature and also will be used ensure all the required configs are provided by mainboard. diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 45d8be8..95eda31 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -67,7 +67,7 @@ config ME_REGION_ALLOW_CPU_READ_ACCESS bool "Allows HOST/CPU read access to ME region" depends on HAVE_IFD_BIN - default y if SOC_INTEL_CSE_LITE_SKU + default y if SOC_INTEL_CSE_LITE_SKU || SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD default n help The config ensures Host has read access to the ME region if it is locked -- To view, visit https://review.coreboot.org/c/coreboot/+/83395?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id6ec19d74237f278e8383c89923523871b2cc2db Gerrit-Change-Number: 83395 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M
by Subrata Banik (Code Review) 11 Jul '24

11 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83394?usp=email ) Change subject: soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M ...................................................................... soc/intel/meteorlake: Conditionally update CSE sync UPDs in FSP-M This patch updates FSP-M UPDs conditionally to ensure CSE firmware updates and VGA initialization control only when `SOC_INTEL_CSE_LITE_SKU` config is enabled. This ensures eSOL rendering is tied to CSE sync performed in coreboot, preventing unnecessary setup when sync is deferred to the payload. Deferring CSE sync to the payload results in the depthcharge screen. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83394 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/meteorlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index ec0bb8d..ec78383 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -454,7 +454,7 @@ sol_type = ELOG_FW_EARLY_SOL_MRC; } - if (is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { vga_init_control = VGA_INIT_CONTROL_ENABLE; sol_type = ELOG_FW_EARLY_SOL_CSE_SYNC; } -- To view, visit https://review.coreboot.org/c/coreboot/+/83394?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffdd4b1be4abba8c57e28542058a575cc6de674c Gerrit-Change-Number: 83394 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility
by Subrata Banik (Code Review) 11 Jul '24

11 Jul '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83393?usp=email ) Change subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility ...................................................................... soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility This patch refactors the handling of CSE CBMEM IDs to enable platforms to choose whether to perform CSE sync operations within coreboot or defer it to the payload. This separation improves code organization, ensuring `cse_lite.c` focuses on coreboot-specific CSE Lite tasks. Now, platforms can select: * `SOC_INTEL_CSE_LITE_SKU` for CSE sync within coreboot * `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` for deferred payload sync This change ensures mutually exclusive options, avoiding unnecessary SPI flash size increases. BUG=b:305898363 TEST=Builds and boots successfully: * google/rex0 with SOC_INTEL_CSE_LITE_SKU * google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83393 Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M payloads/libpayload/libc/coreboot.c M src/soc/intel/common/block/cse/Makefile.mk M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/cse/cse_sync_payload.c 4 files changed, 32 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 7873426..1d914c5 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -262,12 +262,14 @@ case CBMEM_ID_MEM_CHIP_INFO: info->mem_chip_base = cbmem_entry->address; break; +#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) case CBMEM_ID_CSE_BP_INFO: info->cse_bp_info = cbmem_entry->address; break; case CBMEM_ID_CSE_INFO: info->cse_info = cbmem_entry->address; break; +#endif default: break; } diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk index 653d674..d41d735 100644 --- a/src/soc/intel/common/block/cse/Makefile.mk +++ b/src/soc/intel/common/block/cse/Makefile.mk @@ -11,6 +11,8 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c +romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) += cse_sync_payload.c + ifeq ($(CONFIG_STITCH_ME_BIN),y) CSE_BP1_BIN := $(objcse)/cse_bp1.bin diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 4e3a446..6c4fed7 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1542,31 +1542,6 @@ } } -static void preram_create_cbmem_cse_info(int is_recovery) -{ - if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) - return; - - /* - * CBMEM_ID_CSE_INFO will be used by the payload to - - * 1. Avoid reading ISH firmware version on consecutive boots. - * 2. Track state of PSR data during CSE downgrade operation. - */ - void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); - if (!temp) - printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); - - /* - * CBMEM_ID_CSE_BP_INFO will be used by the payload to avoid reading CSE - * boot partition information on consecutive boots. - */ - temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp)); - if (!temp) - printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n"); -} - -CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info); - static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) diff --git a/src/soc/intel/common/block/cse/cse_sync_payload.c b/src/soc/intel/common/block/cse/cse_sync_payload.c new file mode 100644 index 0000000..5c816d1 --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_sync_payload.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <intelblocks/cse.h> +#include <intelblocks/cse_lite.h> + +static void preram_create_cbmem_cse_info_for_payload(int is_recovery) +{ + /* + * CBMEM_ID_CSE_INFO will be used by the payload to - + * 1. Keep ISH firmware version on consecutive boots. + * 2. Track state of PSR data during CSE downgrade operation. + */ + void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); + + /* + * CBMEM_ID_CSE_BP_INFO will be used by the payload to keep CSE + * boot partition information on consecutive boots. + */ + temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n"); +} + +CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info_for_payload); -- To view, visit https://review.coreboot.org/c/coreboot/+/83393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Gerrit-Change-Number: 83393 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: Update amd_blobs submodule to upstream main
by Matt DeVillier (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Matt DeVillier. Hello Felix Singer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83413?usp=email to look at the new patch set (#2). Change subject: Update amd_blobs submodule to upstream main ...................................................................... Update amd_blobs submodule to upstream main Updating from commit id ae5fc7d: 2024-03-15 19:58:57 +0100 - (picasso: Update PSP fw to version 00.08.14.7B) to commit id 26c5729: 2024-07-10 10:10:50 -0500 - (CZN: Update SMU fw to 64.72.0) This brings in 2 new commits: 26c5729 CZN: Update SMU fw to 64.72.0 942adff Add VanGogh blobs Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/83413/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c699379a196a0819201f7a6c9f1b3319edef4ff Gerrit-Change-Number: 83413 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>

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[XS] Change in coreboot[main]: amdfwtool: make fields unsigned
by Raul Rangel (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, George Burgess, Martin L Roth. Raul Rangel has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email ) Change subject: amdfwtool: make fields unsigned ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 2 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: George Burgess <gbiv(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Jul 2024 15:13:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: amdfwtool: make fields unsigned
by Matt DeVillier (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, George Burgess, Martin L Roth, Raul Rangel. Matt DeVillier has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email ) Change subject: amdfwtool: make fields unsigned ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 2 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: George Burgess <gbiv(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Jul 2024 14:59:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake/romstage: Update PchHdaSdiEnable for AlderLakeN
by Subrata Banik (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/83428?usp=email ) Change subject: soc/intel/alderlake/romstage: Update PchHdaSdiEnable for AlderLakeN ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/83428/comment/e9938999_103028ca?us… : PS1, Line 254: #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) u r basically limiting !ADL-N to override PchHdaSdiEnable UPDs. Why so? -- To view, visit https://review.coreboot.org/c/coreboot/+/83428?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia413588e75fbbc11440d1cdf81532ef89f4dcf1e Gerrit-Change-Number: 83428 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Jul 2024 14:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: amdfwtool: make fields unsigned
by George Burgess (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, Martin L Roth, Matt DeVillier, Raul Rangel. George Burgess has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email ) Change subject: amdfwtool: make fields unsigned ...................................................................... Patch Set 2: (1 comment) File util/amdfwtool/amdfwtool.h: https://review.coreboot.org/c/coreboot/+/83412/comment/3dbdc6f8_306c2fd3?us… : PS1, Line 146: int > Maybe just change this to an `unsigned int`? Done. I also modified `reserved`, since other bitfields in this file seem to follow the "merged bitfields should all be the same type," convention. -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 2 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Jul 2024 14:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org>

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[XS] Change in coreboot[main]: amdfwtool: make fields unsigned
by George Burgess (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, George Burgess, Martin L Roth, Matt DeVillier. Hello Felix Held, Fred Reitberger, Martin L Roth, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83412?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: make fields unsigned ...................................................................... amdfwtool: make fields unsigned The value stored in `gen` is only ever `1` or `0`. Storing `1` causes Clang to warn, since the only valid values for a 1-bit int are -1 and 0: ``` amdfwtool.c:1487:27: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] 1487 | amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; ``` TEST=Rebuilt coreboot; no warning was emitted. Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Signed-off-by: George Burgess IV <gbiv(a)google.com> --- M util/amdfwtool/amdfwtool.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83412/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 2 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: George Burgess <gbiv(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: amdfwtool: adjust sign of constant
by Raul Rangel (Code Review) 11 Jul '24

11 Jul '24

Attention is currently required from: Felix Held, Fred Reitberger, George Burgess, Martin L Roth, Matt DeVillier. Raul Rangel has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email ) Change subject: amdfwtool: adjust sign of constant ...................................................................... Patch Set 1: (1 comment) File util/amdfwtool/amdfwtool.h: https://review.coreboot.org/c/coreboot/+/83412/comment/b35cf07d_1b3eeedb?us… : PS1, Line 146: int Maybe just change this to an `unsigned int`? -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 1 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: George Burgess <gbiv(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 11 Jul 2024 14:35:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit July 2024