coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: amdfwtool: make fields unsigned
by Felix Held (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Fred Reitberger, George Burgess, Martin L Roth. Felix Held has posted comments on this change by George Burgess. ( https://review.coreboot.org/c/coreboot/+/83412?usp=email ) Change subject: amdfwtool: make fields unsigned ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83412?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd83be8302e8a717db7e7dc86a403b5648976586 Gerrit-Change-Number: 83412 Gerrit-PatchSet: 2 Gerrit-Owner: George Burgess <gbiv(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: George Burgess <gbiv(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 16:01:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/byra: Add VBTs for variants missing them
by Matt DeVillier (Code Review) 12 Jul '24

12 Jul '24

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83434?usp=email ) Change subject: mb/google/byra: Add VBTs for variants missing them ...................................................................... mb/google/byra: Add VBTs for variants missing them Several brya variants were missing VBT files, add and select them in Kconfig. Also select in Kconfig for VELL, which already had a VBT but was not using/selecting it. TEST=build/boot google/brya (marasov), verify display init functional / payload screen shown. Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/variants/constitution/data.vbt A src/mainboard/google/brya/variants/glassway/data.vbt A src/mainboard/google/brya/variants/marasov/data.vbt A src/mainboard/google/brya/variants/omnigul/data.vbt A src/mainboard/google/brya/variants/uldren/data.vbt 6 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/83434/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 6edd2af..e235fec 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -208,6 +208,7 @@ config BOARD_GOOGLE_CONSTITUTION select BOARD_GOOGLE_BASEBOARD_BRASK select CHROMEOS_WIFI_SAR if CHROMEOS + select INTEL_GMA_HAVE_VBT select MEMORY_SOLDERDOWN select SOC_INTEL_RAPTORLAKE @@ -273,10 +274,11 @@ config BOARD_GOOGLE_GLASSWAY select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG - select CHROMEOS_WIFI_SAR if CHROMEOS + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_GOTHRAX select BOARD_GOOGLE_BASEBOARD_NISSA @@ -334,6 +336,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS @@ -378,6 +381,7 @@ select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS @@ -552,12 +556,14 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_CS42L42 select HAVE_WWAN_POWER_SEQUENCE + select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_I2C_CS35L53 + select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_GOOGLE_VOLMAR diff --git a/src/mainboard/google/brya/variants/constitution/data.vbt b/src/mainboard/google/brya/variants/constitution/data.vbt new file mode 100644 index 0000000..044d25b --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/glassway/data.vbt b/src/mainboard/google/brya/variants/glassway/data.vbt new file mode 100644 index 0000000..ba47065 --- /dev/null +++ b/src/mainboard/google/brya/variants/glassway/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/marasov/data.vbt b/src/mainboard/google/brya/variants/marasov/data.vbt new file mode 100644 index 0000000..4b801b1 --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/omnigul/data.vbt b/src/mainboard/google/brya/variants/omnigul/data.vbt new file mode 100644 index 0000000..c37834d --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/data.vbt Binary files differ diff --git a/src/mainboard/google/brya/variants/uldren/data.vbt b/src/mainboard/google/brya/variants/uldren/data.vbt new file mode 100644 index 0000000..e2fb5d2 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldren/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/83434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432 Gerrit-Change-Number: 83434 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility
by Subrata Banik (Code Review) 12 Jul '24

12 Jul '24

Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83393?usp=email ) Change subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/83393/comment/2551d301_cecf171a?us… : PS2, Line 265: #if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) > Why would you check for a coreboot Kconfig option in libpayload? I am puzzled that it even compiles. I would assume it is enough to check for the CBMEM_ID's since they are not existing if the option hasn't been supplied during the coreboot build. hmm, valid point. let me drop the CPP -- To view, visit https://review.coreboot.org/c/coreboot/+/83393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Gerrit-Change-Number: 83393 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 15:01:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>

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[M] Change in coreboot[main]: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility
by Maximilian Brune (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Subrata Banik. Maximilian Brune has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83393?usp=email ) Change subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility ...................................................................... Patch Set 2: (1 comment) File payloads/libpayload/libc/coreboot.c: https://review.coreboot.org/c/coreboot/+/83393/comment/c67ae668_3ccbb920?us… : PS2, Line 265: #if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) Why would you check for a coreboot Kconfig option in libpayload? I am puzzled that it even compiles. I would assume it is enough to check for the CBMEM_ID's since they are not existing if the option hasn't been supplied during the coreboot build. -- To view, visit https://review.coreboot.org/c/coreboot/+/83393?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4 Gerrit-Change-Number: 83393 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 14:32:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Return resource count for create_ioat_domain
by Angel Pons (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83195?usp=email ) Change subject: soc/intel/xeon_sp/spr: Return resource count for create_ioat_domain ...................................................................... Patch Set 6: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/83195/comment/614f9805_778a3a4f?us… : PS6, Line 63: unsigned int index = 0; This should be initialised to the value of `res_count` if valid, and only fall back to 0 if it's NULL: ```suggestion unsigned int index = res_count ? *res_count : 0; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/83195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e719ae8407c7f31f88dbb407f003e2ded8f0faf Gerrit-Change-Number: 83195 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 12:45:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/riven: add fw_config probe for storage devices
by Felix Held (Code Review) 12 Jul '24

12 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83405?usp=email ) Change subject: mb/google/nissa/var/riven: add fw_config probe for storage devices ...................................................................... mb/google/nissa/var/riven: add fw_config probe for storage devices 1. Add STORAGE_UNKNOWN fw_config to enable all storage devices, this is used for the first boot in factory. 2. Add fw_config probe to enable/disable devices in devicetree instead of variant.c, it can avoid suspend(s0ix) fail issue. BUG=b:328580882 TEST=On riven eMMC and UFS SKUs, boot to OS and run `suspend_stress_test -c 10` pass. Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb M src/mainboard/google/brya/variants/riven/Makefile.mk M src/mainboard/google/brya/variants/riven/fw_config.c M src/mainboard/google/brya/variants/riven/overridetree.cb D src/mainboard/google/brya/variants/riven/variant.c 5 files changed, 16 insertions(+), 35 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 2ab9a3d..aac4bca 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -11,6 +11,7 @@ option STORAGE_EMMC 0 option STORAGE_NVME 1 option STORAGE_UFS 2 + option STORAGE_UNKNOWN 3 end end diff --git a/src/mainboard/google/brya/variants/riven/Makefile.mk b/src/mainboard/google/brya/variants/riven/Makefile.mk index 86ba20d..8ae0e3b 100644 --- a/src/mainboard/google/brya/variants/riven/Makefile.mk +++ b/src/mainboard/google/brya/variants/riven/Makefile.mk @@ -4,5 +4,4 @@ romstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c -ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/riven/fw_config.c b/src/mainboard/google/brya/variants/riven/fw_config.c index 7967282..b22463f 100644 --- a/src/mainboard/google/brya/variants/riven/fw_config.c +++ b/src/mainboard/google/brya/variants/riven/fw_config.c @@ -90,9 +90,11 @@ ARRAY_SIZE(stylus_disable_pads)); } - if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { - printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); - gpio_padbased_override(padbased_table, emmc_disable_pads, + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, ARRAY_SIZE(emmc_disable_pads)); + } } } diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index 796a79c..301d72a 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -478,14 +478,22 @@ end end device ref pcie_rp7 off end # PCIE7 no SD card - device ref emmc on end + device ref emmc on + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_EMMC + end device ref ish on chip drivers/intel/ish register "add_acpi_dma_property" = "true" device generic 0 on end end + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS end - device ref ufs on end + device ref ufs on + probe STORAGE STORAGE_UNKNOWN + probe STORAGE STORAGE_UFS + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] diff --git a/src/mainboard/google/brya/variants/riven/variant.c b/src/mainboard/google/brya/variants/riven/variant.c deleted file mode 100644 index 937215c..0000000 --- a/src/mainboard/google/brya/variants/riven/variant.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <baseboard/variants.h> -#include <console/console.h> -#include <device/device.h> -#include <fw_config.h> - -void variant_devtree_update(void) -{ - struct device *emmc = DEV_PTR(emmc); - struct device *ufs = DEV_PTR(ufs); - struct device *ish = DEV_PTR(ish); - - if (!fw_config_is_provisioned()) { - printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); - return; - } - - if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { - printk(BIOS_INFO, "eMMC disabled by fw_config\n"); - emmc->enabled = 0; - } - - if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { - printk(BIOS_INFO, "UFS disabled by fw_config\n"); - ufs->enabled = 0; - ish->enabled = 0; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/83405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183 Gerrit-Change-Number: 83405 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brask/var/bujia: Disable thunderbolt
by Felix Held (Code Review) 12 Jul '24

12 Jul '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83402?usp=email ) Change subject: mb/google/brask/var/bujia: Disable thunderbolt ...................................................................... mb/google/brask/var/bujia: Disable thunderbolt Bujia does not support Thunderbolt anymore, therefore disable related TBT setting. The bujia fit image CL, cf. chrome-internal:7468938. BUG=b:349923139 BRANCH=firmware-brya-14505.B TEST= USE="-project_all project_bujia" emerge-brask coreboot. Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922 Signed-off-by: Shon <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402 Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/bujia/overridetree.cb 1 file changed, 2 insertions(+), 7 deletions(-) Approvals: Derek Huang: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index bf60101..61d9525 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -151,16 +151,11 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end #NVME + device ref tbt_pcie_rp0 off end device ref tbt_pcie_rp1 off end device ref tbt_pcie_rp2 off end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end + device ref tcss_dma0 off end device ref tcss_dma1 off end device ref cnvi_wifi on chip drivers/wifi/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/83402?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922 Gerrit-Change-Number: 83402 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/dedede: Create awasuki variant
by Tongtong Pan (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Dolan Liu, Eric Lai, Lawrence Chang, Paul Menzel. Tongtong Pan has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/83376?usp=email ) Change subject: mb/google/dedede: Create awasuki variant ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83376/comment/f2d69992_092ced79?us… : PS8, Line 12: (Auto-Generated by create_coreboot_variant.sh version 4.5.0). > Please put the period/dot before the ). Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83376?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0 Gerrit-Change-Number: 83376 Gerrit-PatchSet: 9 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 08:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/dedede/variants/awasuki: Generate 3 RAM IDs
by Weimin Wu (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Eric Lai, Lawrence Chang, Tongtong Pan. Weimin Wu has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/83427?usp=email ) Change subject: mb/google/dedede/variants/awasuki: Generate 3 RAM IDs ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Gerrit-Change-Number: 83427 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 08:23:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/dedede/variants/awasuki: Generate 3 RAM IDs
by Tongtong Pan (Code Review) 12 Jul '24

12 Jul '24

Attention is currently required from: Eric Lai, Lawrence Chang, Weimin Wu. Tongtong Pan has posted comments on this change by Tongtong Pan. ( https://review.coreboot.org/c/coreboot/+/83427?usp=email ) Change subject: mb/google/dedede/variants/awasuki: Generate 3 RAM IDs ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f Gerrit-Change-Number: 83427 Gerrit-PatchSet: 3 Gerrit-Owner: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 12 Jul 2024 08:22:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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