Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83438?usp=email )
Change subject: soc/amd/glinda/include/gpio: update GPIO HID to AMDI0030
......................................................................
soc/amd/glinda/include/gpio: update GPIO HID to AMDI0030
The UEFI reference firmware uses AMDI0030 instead of AMD0030 as HID for
the GPIO controller.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I8dd48d7d9cf3f6d75853bb825e5ddc32bba430b8
---
M src/soc/amd/glinda/include/soc/gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/83438/1
diff --git a/src/soc/amd/glinda/include/soc/gpio.h b/src/soc/amd/glinda/include/soc/gpio.h
index 42d8439..3104889 100644
--- a/src/soc/amd/glinda/include/soc/gpio.h
+++ b/src/soc/amd/glinda/include/soc/gpio.h
@@ -3,7 +3,7 @@
#ifndef AMD_GLINDA_GPIO_H
#define AMD_GLINDA_GPIO_H
-#define GPIO_DEVICE_NAME "AMD0030"
+#define GPIO_DEVICE_NAME "AMDI0030"
#define GPIO_DEVICE_DESC "GPIO Controller"
#ifndef __ACPI__
--
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Gerrit-Change-Id: I8dd48d7d9cf3f6d75853bb825e5ddc32bba430b8
Gerrit-Change-Number: 83438
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Attention is currently required from: Eric Lai, Maximilian Brune, Nick Vaccaro.
Hello Eric Lai, Maximilian Brune, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83436?usp=email
to look at the new patch set (#2).
Change subject: libpayload: Unconditionally handle "CBMEM_ID_CSE_*" entries
......................................................................
libpayload: Unconditionally handle "CBMEM_ID_CSE_*" entries
This change removes the unnecessary conditional compilation around
CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in
cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms
with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without
this config option won't encounter these IDs when calling
cb_parse_cbmem_entry().
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M payloads/libpayload/libc/coreboot.c
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/83436/2
--
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Gerrit-Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Gerrit-Change-Number: 83436
Gerrit-PatchSet: 2
Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
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Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/83393?usp=email )
Change subject: soc/intel/cmn/cse: Refactor CBMEM ID handling for flexibility
......................................................................
Patch Set 2:
(1 comment)
File payloads/libpayload/libc/coreboot.c:
https://review.coreboot.org/c/coreboot/+/83393/comment/38beba20_d2165708?us… :
PS2, Line 265: #if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
> > Why would you check for a coreboot Kconfig option in libpayload? I am puzzled that it even compiles. I would assume it is enough to check for the CBMEM_ID's since they are not existing if the option hasn't been supplied during the coreboot build.
>
> hmm, valid point. let me drop the CPP
CB:83436 , please help to review the code
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Gerrit-Change-Id: I74f70959715f9fd6d4d298faf310592874cc35d4
Gerrit-Change-Number: 83393
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
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Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Comment-Date: Fri, 12 Jul 2024 17:15:31 +0000
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Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>
Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com>
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83436?usp=email )
Change subject: libpayload: Unconditionally handle CBMEM_ID_CSE_ entries*
......................................................................
libpayload: Unconditionally handle CBMEM_ID_CSE_ entries*
This change removes the unnecessary conditional compilation around
CBMEM_ID_CSE_BP_INFO and CBMEM_ID_CSE_INFO handling in
cb_parse_cbmem_entry. These CBMEM IDs are only relevant on platforms
with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD enabled, and platforms without
this config option won't encounter these IDs when calling
cb_parse_cbmem_entry().
BUG=b:305898363
TEST=Builds and boots successfully:
* google/rex0 with SOC_INTEL_CSE_LITE_SKU
* google/rex64 with SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD
Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M payloads/libpayload/libc/coreboot.c
1 file changed, 0 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/83436/1
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 1d914c5..7873426 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -262,14 +262,12 @@
case CBMEM_ID_MEM_CHIP_INFO:
info->mem_chip_base = cbmem_entry->address;
break;
-#if CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)
case CBMEM_ID_CSE_BP_INFO:
info->cse_bp_info = cbmem_entry->address;
break;
case CBMEM_ID_CSE_INFO:
info->cse_info = cbmem_entry->address;
break;
-#endif
default:
break;
}
--
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Gerrit-Change-Id: Icf056f8426015e99509be5f5a67cb66468645cd9
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Elyes Haouas has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/83435?usp=email )
Change subject: [Only for test] define NULL as ((nullptr_t)0)
......................................................................
[Only for test] define NULL as ((nullptr_t)0)
nullptr_t added to GCC-14, let give it a shot (just for test).
Change-Id: Ia0b91cf998748b496d2650475ed0fd010e6e9abd
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/drivers/intel/fsp2_0/temp_ram_exit.c
M src/include/stddef.h
M src/lib/thread.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/common/block/i2c/i2c.c
M tests/lib/imd-test.c
M tests/lib/imd_cbmem-test.c
7 files changed, 13 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/83435/3
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Attention is currently required from: Felix Singer.
Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83411?usp=email )
Change subject: mb/google/drallion: Don't enable DPTF PCI device
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83411/comment/8a62dfeb_b70b246c?us… :
PS1, Line 10: 2nd TCPU ACPI device
> Where is the first TCPU coming from?
I forget offhand, but can go back and check again
> And any idea how devices like touchpad and touchscreen are related to it?
as per the commit msg, the duplicate TCPU device in the SSDT causes Windows to stop processing the entire SSDT, and because the touchpad/screen are defined there, they are not functional
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Felix Singer has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83411?usp=email )
Change subject: mb/google/drallion: Don't enable DPTF PCI device
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83411/comment/8de65432_ced796a1?us… :
PS1, Line 10: 2nd TCPU ACPI device
Where is the first TCPU coming from? And any idea how devices like touchpad and touchscreen are related to it?
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Attention is currently required from: Felix Singer.
Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/83410?usp=email )
Change subject: mb/google/puff: Use auto fan control
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/puff/Kconfig:
https://review.coreboot.org/c/coreboot/+/83410/comment/06433be1_15f1fa1a?us… :
PS1, Line 17: select EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL
> Since this should be applied for non-ChromeOS builds, shouldn't this be conditional on !CHROMEOS? […]
Fix applied.
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