coreboot-gerrit June 2024

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[XS] Change in coreboot[main]: util/intelp2m/platforms: Fix DW register number before clear it
by Felix Held (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Felix Singer, Maxim. Felix Held has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83002?usp=email ) Change subject: util/intelp2m/platforms: Fix DW register number before clear it ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83002?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91e74d65977bd5e10589530258d1709ea33f1af5 Gerrit-Change-Number: 83002 Gerrit-PatchSet: 2 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 16:06:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/emulation/qemu: Configure TSEG size
by Felix Held (Code Review) 21 Jun '24

21 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83114?usp=email ) Change subject: mb/emulation/qemu: Configure TSEG size ...................................................................... mb/emulation/qemu: Configure TSEG size Configure TSEG size by reading CONFIG_SMM_TSEG_SIZE in romstage. The remaining Qemu code can already handle the bigger TSEG region. TEST: Increased TSEG to 8MiB. Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83114 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-q35/romstage.c 2 files changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 221a7ba..e1469d6 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -31,6 +31,11 @@ endchoice +config SMM_TSEG_SIZE + hex + depends on SMM_TSEG + default 0x100000 + config MAX_CPUS int default 32 if SMM_TSEG diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index ff06640..d4700d5 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -7,6 +7,8 @@ #include "q35.h" +#define TSEG_SZ_MASK (3 << 1) + void mainboard_romstage_entry(void) { i82801ix_early_init(); @@ -14,5 +16,20 @@ if (!CONFIG(BOOTBLOCK_CONSOLE)) mainboard_machine_check(); + /* Configure requested TSEG size */ + switch (CONFIG_SMM_TSEG_SIZE) { + case 1 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 0 << 1); + break; + case 2 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 1 << 1); + break; + case 8 * MiB: + pci_update_config8(HOST_BRIDGE, ESMRAMC, ~TSEG_SZ_MASK, 2 << 1); + break; + default: + printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE); + } + cbmem_recovery(0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/83114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ae5ac93ecca83ae9c319c666aac844bbd5b259f Gerrit-Change-Number: 83114 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: commonlib/fsp_relocate: Add PE32+ support
by Felix Held (Code Review) 21 Jun '24

21 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82680?usp=email ) Change subject: commonlib/fsp_relocate: Add PE32+ support ...................................................................... commonlib/fsp_relocate: Add PE32+ support Add support for PE32+ binaries which can be found on X64 UEFI builds. TEST: Able to relocate and boot a X64 FSP. Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82680 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/fsp_relocate.c 1 file changed, 39 insertions(+), 22 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index f57e278..0bf50b4 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -160,16 +160,17 @@ static int pe_relocate(uintptr_t new_addr, void *pe, void *fsp, size_t fih_off) { - EFI_IMAGE_NT_HEADERS32 *peih; + EFI_IMAGE_OPTIONAL_HEADER_UNION *peih; EFI_IMAGE_DOS_HEADER *doshdr; EFI_IMAGE_OPTIONAL_HEADER32 *ophdr; + EFI_IMAGE_OPTIONAL_HEADER64 *ophdr64; FSP_INFO_HEADER *fih; uint32_t roffset, rsize; uint32_t offset; uint8_t *pe_base = pe; - uint32_t image_base; - uint32_t img_base_off; - uint32_t delta; + uint64_t image_base; + uint64_t img_base_off; + uint64_t delta; doshdr = pe; if (read_le16(&doshdr->e_magic) != EFI_IMAGE_DOS_SIGNATURE) { @@ -179,15 +180,20 @@ peih = relative_offset(pe, doshdr->e_lfanew); - if (read_le32(&peih->Signature) != EFI_IMAGE_NT_SIGNATURE) { + if (read_le32(&peih->Pe32.Signature) != EFI_IMAGE_NT_SIGNATURE) { printk(BIOS_ERR, "Invalid PE32 header\n"); return -1; } - ophdr = &peih->OptionalHeader; + ophdr = &peih->Pe32.OptionalHeader; + ophdr64 = &peih->Pe32Plus.OptionalHeader; - if (read_le16(&ophdr->Magic) != EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) { - printk(BIOS_ERR, "No support for non-PE32 images\n"); + if (read_le16(&ophdr->Magic) == EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC) { + ophdr64 = NULL; + } else if (read_le16(&ophdr64->Magic) == EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC) { + ophdr = NULL; + } else { + printk(BIOS_ERR, "No support for non-PE32/PE32+ images\n"); return -1; } @@ -197,21 +203,26 @@ return -1; } image_base = read_le32(&fih->ImageBase); - printk(FSP_DBG_LVL, "FSP InfoHdr Image Base is %x\n", image_base); + printk(FSP_DBG_LVL, "FSP InfoHdr Image Base is %" PRIX64"\n", image_base); delta = new_addr - image_base; - img_base_off = read_le32(&ophdr->ImageBase); - printk(FSP_DBG_LVL, "lfanew 0x%x, delta-0x%x, FSP Base 0x%x, NT32ImageBase 0x%x, offset 0x%x\n", + img_base_off = ophdr ? read_le32(&ophdr->ImageBase) : read_le64(&ophdr64->ImageBase); + printk(FSP_DBG_LVL, "lfanew 0x%x, delta-0x%" PRIX64 ", FSP Base 0x%" PRIX64 ", NT32ImageBase 0x%" PRIX64 ", offset 0x%" PRIX64 "\n", read_le32(&doshdr->e_lfanew), delta, image_base, img_base_off, - (uint32_t)((uint8_t *)&ophdr->ImageBase - pe_base)); + (uint64_t)((uint8_t *)(uintptr_t)img_base_off - pe_base)); - printk(FSP_DBG_LVL, "relocating PE32 image at addr - 0x%" PRIxPTR "\n", new_addr); - rsize = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size); - roffset = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress); + printk(FSP_DBG_LVL, "relocating PE32%s image at addr - 0x%" PRIxPTR "\n", ophdr ? "" : "+", new_addr); + if (ophdr) { + rsize = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size); + roffset = read_le32(&ophdr->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress); + } else { + rsize = read_le32(&ophdr64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].Size); + roffset = read_le32(&ophdr64->DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_BASERELOC].VirtualAddress); + } + printk(FSP_DBG_LVL, "relocation table at offset-%x,size=%x\n", roffset, rsize); - // TODO - add support for PE32+ also offset = roffset; while (offset < (roffset + rsize)) { @@ -234,20 +245,23 @@ uint16_t roff = reloc_offset(rdata[i]); uint16_t rtype = reloc_type(rdata[i]); uint32_t aoff = vaddr + roff; - uint32_t val; - printk(FSP_DBG_LVL, "\t\treloc type %x offset %x aoff %x, base-0x%x\n", + uint64_t val; + printk(FSP_DBG_LVL, "\t\treloc type %x offset %x aoff %x, base-0x%" PRIX64 "\n", rtype, roff, aoff, img_base_off); switch (rtype) { case EFI_IMAGE_REL_BASED_ABSOLUTE: continue; case EFI_IMAGE_REL_BASED_HIGHLOW: val = read_le32(&pe_base[aoff]); - printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", + printk(FSP_DBG_LVL, "Adjusting %p %" PRIX64 " -> %" PRIX64 "\n", &pe_base[aoff], val, val + delta); write_le32(&pe_base[aoff], val + delta); break; case EFI_IMAGE_REL_BASED_DIR64: - printk(BIOS_ERR, "Unsupported DIR64\n"); + val = read_le64(&pe_base[aoff]); + printk(FSP_DBG_LVL, "Adjusting %p %" PRIX64 " -> %" PRIX64 "\n", + &pe_base[aoff], val, val + delta); + write_le64(&pe_base[aoff], val + delta); break; default: printk(BIOS_ERR, "Unsupported relocation type %d\n", @@ -257,10 +271,13 @@ } offset += sizeof(*rdata) * rnum; } - printk(FSP_DBG_LVL, "Adjust Image Base %x->%x\n", + printk(FSP_DBG_LVL, "Adjust Image Base %" PRIX64 "->%" PRIX64 "\n", img_base_off, img_base_off + delta); img_base_off += delta; - write_le32(&ophdr->ImageBase, img_base_off); + if (ophdr) + write_le32(&ophdr->ImageBase, img_base_off); + else + write_le64(&ophdr64->ImageBase, img_base_off); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/82680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22586834d7c9f3ab3a5e31bba957584587ec14e0 Gerrit-Change-Number: 82680 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill wit...
by Subrata Banik (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Kapil Porwal. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/83103?usp=email ) Change subject: soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE info ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/83103/comment/83be4aa6_2424c322?us… : PS8, Line 1555: void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); : if (!temp) : printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); @kapilporwal@google.com i missed this during review. what is the underlying assumption here that we still send CSE basic information cmd even in coreboot (although we select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD) to collect ISH fw information, PSR data, CSE boot partition information etc. That means, we can't get rid of sending HECI cmd from coreboot ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Gerrit-Change-Number: 83103 Gerrit-PatchSet: 8 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 15:32:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: acpigen_ps2_keybd: Support an Accessibility key
by Aseda Aboagye (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Cliff Huang, Forest Mittelberg, Lance Zhao, Paul Menzel, Tim Wawrzynczak. Aseda Aboagye has posted comments on this change by Aseda Aboagye. ( https://review.coreboot.org/c/coreboot/+/82996?usp=email ) Change subject: acpigen_ps2_keybd: Support an Accessibility key ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82996/comment/c71480eb_2152db2e?us… : PS2, Line 15: Linux kernel with patches > Please reference them. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Gerrit-Change-Number: 82996 Gerrit-PatchSet: 4 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 15:31:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: acpigen_ps2_keybd: Support an Accessibility key
by Aseda Aboagye (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Aseda Aboagye, Cliff Huang, Forest Mittelberg, Lance Zhao, Tim Wawrzynczak. Hello Caveh Jalali, Cliff Huang, Forest Mittelberg, Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82996?usp=email to look at the new patch set (#4). Change subject: acpigen_ps2_keybd: Support an Accessibility key ...................................................................... acpigen_ps2_keybd: Support an Accessibility key Add support for an Accessibility key. HUTRR116 added support for a new usage titled "System Accessibility Binding" which toggles a system-wide bound accessibility UI or command. BUG=b:333095388 TEST=Build and flash a board that contains an accessibility key. Verify that KEY_ACCESSIBILITY is generated in the Linux kernel with patches[0] that add this new event code using `evtest`. ``` Testing ... (interrupt to exit) Event: time 1718924048.882841, -------------- SYN_REPORT ------------ Event: time 1718924054.062428, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.062428, type 1 (EV_KEY), code 590 (?), value 1 Event: time 1718924054.062428, -------------- SYN_REPORT ------------ Event: time 1718924054.195904, type 4 (EV_MSC), code 4 (MSC_SCAN), value a9 Event: time 1718924054.195904, type 1 (EV_KEY), code 590 (?), value 0 Event: time 1718924054.195904, -------------- SYN_REPORT ------------ ``` [0] - https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git/commit/?id=0c7d… Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/acpi/acpigen_ps2_keybd.c M src/ec/google/chromeec/ec_acpi.c M src/include/acpi/acpigen_ps2_keybd.h 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/82996/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Gerrit-Change-Number: 82996 Gerrit-PatchSet: 4 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com>

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[S] Change in coreboot[main]: util: Move remainings from ipqheader to qualcomm directory
by Felix Held (Code Review) 21 Jun '24

21 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83028?usp=email ) Change subject: util: Move remainings from ipqheader to qualcomm directory ...................................................................... util: Move remainings from ipqheader to qualcomm directory With commit 101098c41a ("sdm845: Combine BB with QC-Sec for ROM boot"), most files from ipqheader were moved to the qualcomm directory. Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83028 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- D util/ipqheader/description.md M util/qualcomm/description.md 2 files changed, 11 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/ipqheader/description.md b/util/ipqheader/description.md deleted file mode 100644 index cfe53e8..0000000 --- a/util/ipqheader/description.md +++ /dev/null @@ -1,8 +0,0 @@ -__ipqheader__ - * _createxbl.py_ - Concatenates XBL segments into one ELF image - `Python` - * _ipqheader.py_ - Returns a packed MBN header image with the - specified base and size `Python` - * _mbncat.py_ - Generate ipq8064 uber SBL `Python` - * *mbn_tools.py* - Contains all MBN Utilities for image generation - `Python` diff --git a/util/qualcomm/description.md b/util/qualcomm/description.md index 22238c6..352ebec 100644 --- a/util/qualcomm/description.md +++ b/util/qualcomm/description.md @@ -1 +1,11 @@ -CMM script to debug Qualcomm coreboot environments. `CMM` +__cmm__ + * CMM script to debug Qualcomm coreboot environments. `CMM` + +__ipqheader__ + * _createxbl.py_ - Concatenates XBL segments into one ELF image + `Python` + * _ipqheader.py_ - Returns a packed MBN header image with the + specified base and size `Python` + * _mbncat.py_ - Generate ipq8064 uber SBL `Python` + * *mbn_tools.py* - Contains all MBN Utilities for image generation + `Python` -- To view, visit https://review.coreboot.org/c/coreboot/+/83028?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e5136bd5ec4fd47bbd93cea2e4614fa63a3bd4e Gerrit-Change-Number: 83028 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[L] Change in coreboot[main]: soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill wit...
by Felix Held (Code Review) 21 Jun '24

21 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83103?usp=email ) Change subject: soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE info ...................................................................... soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE info Currently, the payload cannot create new CBMEM entries as there is no such infrastructure available. The Intel CSE driver in the payload needs below CBMEM entries - 1. CBMEM_ID_CSE_INFO to - a. Avoid reading ISH firmware version on consecutive boots. b. Track state of PSR data during CSE downgrade operation. 2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition information on consecutive boots. The idea here is to create required CBMEM entries in coreboot so that later they can be consumed by the payload. BUG=b:305898363 TEST=Store CSE version info in CBMEM area in depthcharge on Screebo Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse_layout.h A src/soc/intel/common/block/include/intelblocks/cse_lite.h 3 files changed, 166 insertions(+), 115 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 6e5b451..4e3a446 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -12,6 +12,7 @@ #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> +#include <intelblocks/cse_lite.h> #include <intelblocks/spi.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -20,121 +21,6 @@ #include "cse_lite_cmos.h" -#define BPDT_HEADER_SZ sizeof(struct bpdt_header) -#define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) -#define SUBPART_HEADER_SZ sizeof(struct subpart_hdr) -#define SUBPART_ENTRY_SZ sizeof(struct subpart_entry) -#define SUBPART_MANIFEST_HDR_SZ sizeof(struct subpart_entry_manifest_header) - -/* Converts bp index to boot partition string */ -#define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") - -/* CSE RW boot partition signature */ -#define CSE_RW_SIGNATURE 0x000055aa - -/* CSE RW boot partition signature size */ -#define CSE_RW_SIGN_SIZE sizeof(uint32_t) - -/* - * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are - * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. - * CSE Lite SKU Image Layout: - * +------------+ +----+------+----+ +-----+------+-----+ - * | CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 | - * +------------+ +----+------+----+ +-----+------+-----+ - */ -#define CSE_MAX_BOOT_PARTITIONS 3 - -/* CSE Lite SKU's valid bootable partition identifiers */ -enum boot_partition_id { - /* RO(BP1) contains recovery/minimal boot firmware */ - RO = 0, - - /* RW(BP2) contains fully functional CSE firmware */ - RW = 1 -}; - -/* - * Boot partition status. - * The status is returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. - */ -enum bp_status { - /* This value is returned when a partition has no errors */ - BP_STATUS_SUCCESS = 0, - - /* - * This value is returned when a partition should be present based on layout, but it is - * not valid. - */ - BP_STATUS_GENERAL_FAILURE = 1, - - /* This value is returned when a partition is not present per initial image layout */ - BP_STATUS_PARTITION_NOT_PRESENT = 2, - - /* - * This value is returned when unexpected issues are detected in CSE Data area - * and CSE TCB-SVN downgrade scenario. - */ - BP_STATUS_DATA_FAILURE = 3, -}; - -/* - * Boot Partition Info Flags - * The flags are returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. - */ -enum bp_info_flags { - /* Redundancy Enabled: It indicates CSE supports RO(BP1) and RW(BP2) regions */ - BP_INFO_REDUNDANCY_EN = 1 << 0, - - /* It indicates RO(BP1) supports Minimal Recovery Mode */ - BP_INFO_MIN_RECOV_MODE_EN = 1 << 1, - - /* - * Read-only Config Enabled: It indicates HW protection to CSE RO region is enabled. - * The option is relevant only if the BP_INFO_MIN_RECOV_MODE_EN flag is enabled. - */ - BP_INFO_READ_ONLY_CFG = 1 << 2, -}; - -/* CSE boot partition entry info */ -struct cse_bp_entry { - /* Boot partition version */ - struct fw_version fw_ver; - - /* Boot partition status */ - uint32_t status; - - /* Starting offset of the partition within CSE region */ - uint32_t start_offset; - - /* Ending offset of the partition within CSE region */ - uint32_t end_offset; - uint8_t reserved[12]; -} __packed; - -/* CSE boot partition info */ -struct cse_bp_info { - /* Number of boot partitions */ - uint8_t total_number_of_bp; - - /* Current boot partition */ - uint8_t current_bp; - - /* Next boot partition */ - uint8_t next_bp; - - /* Boot Partition Info Flags */ - uint8_t flags; - - /* Boot Partition Entry Info */ - struct cse_bp_entry bp_entries[CSE_MAX_BOOT_PARTITIONS]; -} __packed; - -struct get_bp_info_rsp { - struct mkhi_hdr hdr; - struct cse_bp_info bp_info; -} __packed; - static struct get_bp_info_rsp cse_bp_info_rsp; enum cse_fw_state { @@ -331,6 +217,9 @@ /* Function to copy PRERAM CSE specific info to pertinent CBMEM. */ static void preram_cse_info_sync_to_cbmem(int is_recovery) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + if (vboot_recovery_mode_enabled() || !CONFIG(SOC_INTEL_STORE_CSE_FW_VERSION)) return; @@ -517,6 +406,9 @@ void cse_fill_bp_info(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + if (vboot_recovery_mode_enabled()) return; @@ -527,6 +419,9 @@ /* Function to copy PRERAM CSE BP info to pertinent CBMEM. */ static void preram_cse_bp_info_sync_to_cbmem(int is_recovery) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + if (vboot_recovery_mode_enabled()) return; @@ -1585,6 +1480,9 @@ */ static void store_ish_version(void) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + if (!ENV_RAMSTAGE) return; @@ -1644,6 +1542,31 @@ } } +static void preram_create_cbmem_cse_info(int is_recovery) +{ + if (!CONFIG(SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD)) + return; + + /* + * CBMEM_ID_CSE_INFO will be used by the payload to - + * 1. Avoid reading ISH firmware version on consecutive boots. + * 2. Track state of PSR data during CSE downgrade operation. + */ + void *temp = cbmem_add(CBMEM_ID_CSE_INFO, sizeof(struct cse_specific_info)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_INFO\n"); + + /* + * CBMEM_ID_CSE_BP_INFO will be used by the payload to avoid reading CSE + * boot partition information on consecutive boots. + */ + temp = cbmem_add(CBMEM_ID_CSE_BP_INFO, sizeof(struct get_bp_info_rsp)); + if (!temp) + printk(BIOS_ERR, "cse_lite: Couldn't create CBMEM_ID_CSE_BP_INFO\n"); +} + +CBMEM_CREATION_HOOK(preram_create_cbmem_cse_info); + static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) diff --git a/src/soc/intel/common/block/include/intelblocks/cse_layout.h b/src/soc/intel/common/block/include/intelblocks/cse_layout.h index 4c88cc5..f5ff632 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_layout.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_layout.h @@ -1,6 +1,9 @@ /* BPDT version 1.7 support */ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef SOC_INTEL_COMMON_CSE_LAYOUT_H +#define SOC_INTEL_COMMON_CSE_LAYOUT_H + #include <sys/types.h> enum bpdt_entry_type { @@ -103,3 +106,11 @@ uint16_t hotfix; } binary_version; } __packed; + +#define BPDT_HEADER_SZ sizeof(struct bpdt_header) +#define BPDT_ENTRY_SZ sizeof(struct bpdt_entry) +#define SUBPART_HEADER_SZ sizeof(struct subpart_hdr) +#define SUBPART_ENTRY_SZ sizeof(struct subpart_entry) +#define SUBPART_MANIFEST_HDR_SZ sizeof(struct subpart_entry_manifest_header) + +#endif // SOC_INTEL_COMMON_CSE_LAYOUT_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_lite.h b/src/soc/intel/common/block/include/intelblocks/cse_lite.h new file mode 100644 index 0000000..46666b6 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_lite.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_CSE_LITE_H +#define SOC_INTEL_COMMON_CSE_LITE_H + +#include <sys/types.h> + +/* Converts bp index to boot partition string */ +#define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") + +/* CSE RW boot partition signature */ +#define CSE_RW_SIGNATURE 0x000055aa + +/* CSE RW boot partition signature size */ +#define CSE_RW_SIGN_SIZE sizeof(uint32_t) + +/* + * CSE Firmware supports 3 boot partitions. For CSE Lite SKU, only 2 boot partitions are + * used and 3rd boot partition is set to BP_STATUS_PARTITION_NOT_PRESENT. + * CSE Lite SKU Image Layout: + * +------------+ +----+------+----+ +-----+------+-----+ + * | CSE REGION | => | RO | DATA | RW | => | BP1 | DATA | BP2 | + * +------------+ +----+------+----+ +-----+------+-----+ + */ +#define CSE_MAX_BOOT_PARTITIONS 3 + +/* CSE Lite SKU's valid bootable partition identifiers */ +enum boot_partition_id { + /* RO(BP1) contains recovery/minimal boot firmware */ + RO = 0, + + /* RW(BP2) contains fully functional CSE firmware */ + RW = 1 +}; + +/* + * Boot partition status. + * The status is returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. + */ +enum bp_status { + /* This value is returned when a partition has no errors */ + BP_STATUS_SUCCESS = 0, + + /* + * This value is returned when a partition should be present based on layout, but it is + * not valid. + */ + BP_STATUS_GENERAL_FAILURE = 1, + + /* This value is returned when a partition is not present per initial image layout */ + BP_STATUS_PARTITION_NOT_PRESENT = 2, + + /* + * This value is returned when unexpected issues are detected in CSE Data area + * and CSE TCB-SVN downgrade scenario. + */ + BP_STATUS_DATA_FAILURE = 3, +}; + +/* + * Boot Partition Info Flags + * The flags are returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. + */ +enum bp_info_flags { + /* Redundancy Enabled: It indicates CSE supports RO(BP1) and RW(BP2) regions */ + BP_INFO_REDUNDANCY_EN = 1 << 0, + + /* It indicates RO(BP1) supports Minimal Recovery Mode */ + BP_INFO_MIN_RECOV_MODE_EN = 1 << 1, + + /* + * Read-only Config Enabled: It indicates HW protection to CSE RO region is enabled. + * The option is relevant only if the BP_INFO_MIN_RECOV_MODE_EN flag is enabled. + */ + BP_INFO_READ_ONLY_CFG = 1 << 2, +}; + +/* CSE boot partition entry info */ +struct cse_bp_entry { + /* Boot partition version */ + struct fw_version fw_ver; + + /* Boot partition status */ + uint32_t status; + + /* Starting offset of the partition within CSE region */ + uint32_t start_offset; + + /* Ending offset of the partition within CSE region */ + uint32_t end_offset; + uint8_t reserved[12]; +} __packed; + +/* CSE boot partition info */ +struct cse_bp_info { + /* Number of boot partitions */ + uint8_t total_number_of_bp; + + /* Current boot partition */ + uint8_t current_bp; + + /* Next boot partition */ + uint8_t next_bp; + + /* Boot Partition Info Flags */ + uint8_t flags; + + /* Boot Partition Entry Info */ + struct cse_bp_entry bp_entries[CSE_MAX_BOOT_PARTITIONS]; +} __packed; + +struct get_bp_info_rsp { + struct mkhi_hdr hdr; + struct cse_bp_info bp_info; +} __packed; + +#endif // SOC_INTEL_COMMON_CSE_LITE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/83103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585 Gerrit-Change-Number: 83103 Gerrit-PatchSet: 8 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_config
by Eric Lai (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Poornima Tom, Subrata Banik. Eric Lai has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83148?usp=email ) Change subject: mb/google/nissa/var/nivviks: Disable CNVi Bluetooth based on fw_config ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83148?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd Gerrit-Change-Number: 83148 Gerrit-PatchSet: 2 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 15:01:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_config
by Eric Lai (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Paul Menzel, Poornima Tom, Subrata Banik, V Sowmya. Eric Lai has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83077?usp=email ) Change subject: mb/google/nissa/var/nivviks: Enable PCIe Wifi GPIOs based on fw_config ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0584e91b5143c6df742961657d242c046409b3a Gerrit-Change-Number: 83077 Gerrit-PatchSet: 11 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 15:00:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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