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Change subject: mb/google/nissa/var/nivviks: Enable Bluetooth for PCIE
......................................................................
Patch Set 8: Code-Review+2
(1 comment)
File src/mainboard/google/brya/variants/nivviks/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83076/comment/c5edd883_aba5fb6d?us… :
PS8, Line 665: probe WIFI_CATEGORY WIFI_7
do you need the reset gpio?
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Change subject: mb/google/nissa/var/nivviks: Enable wifi7 on pcie root port
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Patch Set 7: Code-Review+2
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Change subject: mb/google/nissa/var/nivviks: Update config for CNVi
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/nissa/var/nivviks: Add fw_config fields for wifi6 and wifi7
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Patch Set 7: Code-Review+2
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Change subject: soc/intel: Adapt crashlog IP to also support 64-bit
......................................................................
Patch Set 22:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83106/comment/92c35018_6b05a5e0?us… :
PS19, Line 14: tested
> I am testing and comparing the boot logs - local copy for testing has src address incremented by 4 .
Acknowledged
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Hello Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: soc/intel: Adapt crashlog IP to also support 64-bit
......................................................................
soc/intel: Adapt crashlog IP to also support 64-bit
This patch extends the crashlog IP support beyond 32-bit mode to
support Intel future generation SoCs, which may require crashlog
support for 64-bit architectures. uintptr_t data type is used for
Address pointers and void* for dereferencing
BUG=b:346676856
TEST=Successfully built Meteor Lake (rex) and tested for google/rex0
and google/rex64 images.
Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com>
---
M src/soc/intel/alderlake/crashlog.c
M src/soc/intel/common/block/crashlog/crashlog.c
M src/soc/intel/common/block/include/intelblocks/crashlog.h
M src/soc/intel/meteorlake/crashlog.c
M src/soc/intel/tigerlake/crashlog_lib.c
5 files changed, 76 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/83106/22
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Change subject: Kconfig: Remove prompt for FW_CONFIG_SOURCE_CHROMEEC_CBI
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/Kconfig:
https://review.coreboot.org/c/coreboot/+/83118/comment/12e27770_9b4b4cd7?us… :
PS1, Line 509: bool "Firmware Configuration Probing"
This looks spurious too. Isn't it that the respective board ports actually need it?
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Change subject: soc/intel/soc: Remove save state handler code
......................................................................
Patch Set 9: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/smihandler.c:
https://review.coreboot.org/c/coreboot/+/83068/comment/0f1d05f7_6629202d?us… :
PS9, Line 89: const smi_handler_t southbridge_smi[32] = {
> Would it make sense to use a macro instead of a constant?
I also wondered, forgot to comment. Why was this changed?
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Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
......................................................................
Patch Set 3: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83136/comment/8ac6c028_1a781f44?us… :
PS3, Line 10: not for PCIe device usage.
Not for DRAM either. It's simply unusable to us, right? I would
write something like "is reserved for unknown devices" (or list
the devices).
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/83136/comment/727e7cc5_0531fc80?us… :
PS3, Line 62: (reserved_mmio <= sr->PciResourceMem32Limit))
Shouldn't align with the if body. i.e. either do
```
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
(reserved_mmio <= sr->PciResourceMem32Limit))
mmio_range(...
```
or
```
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
(reserved_mmio <= sr->PciResourceMem32Limit))
mmio_range(...
```
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/83136/comment/9d8f7e70_ea69c2af?us… :
PS3, Line 143: (reserved_mmio <= sr->PciResourceMem32Limit)) {
Same alignment issue.
https://review.coreboot.org/c/coreboot/+/83136/comment/81361cfb_b27b222c?us… :
PS3, Line 146: index++;
This could be handled with an optional pointer argument to create_ioat_domain(),
to return the current index. Not sure if that would look better, though, so leaving
resolved.
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