coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3527 discussions

[XS] Change in coreboot[main]: Makefile.mk: Put site-local path first
by Felix Held (Code Review) 24 Jun '24

24 Jun '24

Felix Held has posted comments on this change by Nikolai Vyssotski. ( https://review.coreboot.org/c/coreboot/+/68799?usp=email ) Change subject: Makefile.mk: Put site-local path first ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: > Breaks inclusion of site-local/Makefile.inc by overwriting subdirs-y. CB:83190 fixes it. ouch, missed that one. thanks for fixing that -- To view, visit https://review.coreboot.org/c/coreboot/+/68799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ea865cd73aba5092a628b0422e5c4121b32fb4d Gerrit-Change-Number: 68799 Gerrit-PatchSet: 6 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 24 Jun 2024 15:08:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>

1 0

[XS] Change in coreboot[main]: mb/google/brox: Add default ACPI brightness levels
by Shelley Chen (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Karthik Ramasubramanian, Matt DeVillier, Shyam Sundar Radjacoumar. Shelley Chen has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/83152?usp=email ) Change subject: mb/google/brox: Add default ACPI brightness levels ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd569b0efef31908edb1b7dc384e60a16fc5bd0c Gerrit-Change-Number: 83152 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 24 Jun 2024 15:05:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: mainboard/google/brox: Add FW_CONFIG and SKU definitions to support l...
by Shelley Chen (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Bob Moragues. Shelley Chen has posted comments on this change by Bob Moragues. ( https://review.coreboot.org/c/coreboot/+/82630?usp=email ) Change subject: mainboard/google/brox: Add FW_CONFIG and SKU definitions to support lotso ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brox/variants/brox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/82630/comment/becc7513_55e3d4c9?us… : PS3, Line 19: option AUDIO_REALTEK_ALC3287 2 I don't think that you want this in brox. This is specific to lotso correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/82630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52cf42b79eff91ab2b4e98a7b5961310e60f2ea7 Gerrit-Change-Number: 82630 Gerrit-PatchSet: 3 Gerrit-Owner: Bob Moragues <moragues(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bob Moragues <moragues(a)google.com> Gerrit-Attention: Bob Moragues <moragues(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Jun 2024 15:04:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: lotso: Update board type to BOARD_TYPE_ULT_ULX
by Shelley Chen (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Karthik Ramasubramanian, Kun Liu, Subrata Banik. Shelley Chen has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/83191?usp=email ) Change subject: lotso: Update board type to BOARD_TYPE_ULT_ULX ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83191?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I049d7c19424f41e83480f4b80bafd6ef8b9e30f6 Gerrit-Change-Number: 83191 Gerrit-PatchSet: 2 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 24 Jun 2024 14:58:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: util/superiotool: Add callback to switch chip-specific selector
by Maxim (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Felix Held, Felix Singer, Michał Żygowski. Maxim has posted comments on this change by Maxim. ( https://review.coreboot.org/c/coreboot/+/83001?usp=email ) Change subject: util/superiotool: Add callback to switch chip-specific selector ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: Another way is to use a special status table - https://review.coreboot.org/c/coreboot/+/83196 -- To view, visit https://review.coreboot.org/c/coreboot/+/83001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icfa0554aabcefd2f681d6b0fade6dbfc1b53a232 Gerrit-Change-Number: 83001 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 24 Jun 2024 14:54:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: [RFC][WIP] util/superiotool: Add extra selectors control
by Maxim (Code Review) 24 Jun '24

24 Jun '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83196?usp=email ) Change subject: [RFC][WIP] util/superiotool: Add extra selectors control ...................................................................... [RFC][WIP] util/superiotool: Add extra selectors control Some chips, have specific selectors (in addition to LDN-register) that affect the register space. At the same time, the utility doesn't provide a simple and convenient method for configuring such selectors (as in the case of LDN-selector) to create a dump, because this may be configured by several fields of the register, and the values of its other fields should not change after setting in the BIOS (fintek [1,2]). To switch register banks using such an extra selector, it is necessary to define a table of its states (which includes the identifier, register index, register mask and selector value) and define a special EXT_SELECTOR macro in the superio_registers table instead of idx[i], and the corresponding def[i] should contain the id of the selector state table with the required value [1, 2]: static extra_selector_state_t esel_table[] = { {.id = 1, .idx = 0x27, .mask = 0xf2, .val = 0x01}, {.id = 2, .idx = 0x27, .mask = 0xf2, .val = 0x00}, } {... EXT_SELECTOR, 0x28,0x2c, EXT_SELECTOR, 0x2c, ...} {... 1, NANA,0x0f, 2, 0x00, ...} The current solution with the esel state table seems to be the safest, since it limits the list of possible selector values. Tested with Fintek F81966 on Asrock IMB-1222 [3]: superiotool r24.05-302-g7d52d9d0f8 Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e LDN 0xfe (Global) idx [27] 02 ... [27] 28 ... 2c [27] 28 ... 2c [27] 28 ... 2c [27] ... val [00] 00 ... [04] 00 ... 00 [08] 03 ... 01 [0c] 59 ... 18 [01] ... def [00] NA ... [04] 00 ... 00 [08] 03 ... 00 [0c] 5b ... 18 [01] ... ... or with -a option: superiotool r24.05-302-g7d52d9d0f8 Found Fintek F81962/F81964/F81966/F81967 (vid=0x3419, id=0x0215) at 0x2e LDN 0xfe (Global) idx def val ============================= [0x27] 0x00 0x00 ESEL[00] ============================= 0x02: (NA) 0x00 ... 0x2d: 0x28 [0x2e] ============================= [0x27] 0x04 0x04 ESEL[01] ============================= 0x28: 0x00 0x00 ... 0x2c: 0x00 0x00 ============================= [0x27] 0x08 0x08 ESEL[02] ============================= 0x28: 0x03 0x03 ... 0x2c: 0x00 [0x01] ============================= [0x27] 0x0c 0x0c ESEL[03] ============================= 0x28: 0x5b [0x59] ... 0x2c: 0x18 0x18 ============================= [0x27] 0x01 0x01 ESEL[04] ============================= 0x29: 0x03 0x03 ... 0x2c: 0x00 0x00 ============================= [0x27] 0x00 0x00 ESEL[00] ============================= ... ESEL[x], where x is the id of the entry in the selector. In print, idx contains the index of the selector register, val is the current value, and def is the value from the status table. In case of an error, if an entry in the table with the specified id does not exist, then [XX] will be printed instead of idx, def and var. The status table looks better than the callback [4], because it standardizes the use of the selector and allows you to set all valid values at once + the code is cleaner, but I still don't really like this solution. In any case, I am limited to only one variable in def[i] from reg_table (I don't want to separate idx and def into different fields, it looks ugly and requires a lot of unnecessary macro constructs This will only create confusion).. Another way is to embed the selector structure directly into 'superio_registers', but this is a lot of changes for all chips. [1] CB:83004 [2] CB:83019 [3] CB:83107 [4] CB:83001 Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/superiotool.c M util/superiotool/superiotool.h 2 files changed, 107 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/83196/1 diff --git a/util/superiotool/superiotool.c b/util/superiotool/superiotool.c index aee5026..837e133 100644 --- a/util/superiotool/superiotool.c +++ b/util/superiotool/superiotool.c @@ -84,22 +84,47 @@ return "<unknown>"; } +static uint8_t set_extra_selector(uint16_t port, const extra_selector_state_t *selector) { + + uint8_t val = regval(port, selector->idx); + val &= selector->mask; + val |= selector->val; + regwrite(port, selector->idx, val); + + return regval(port, selector->idx) & (~selector->mask); +} + +static const extra_selector_state_t* get_ext_sel_state_entry( + const extra_selector_state_t table[], uint8_t table_size, int16_t entry_num) { + if (table == NULL) { + return NULL; + } + for (int i = 0; i < table_size; i++) { + if (table[i].id == entry_num) + return &table[i]; + } + return NULL; +} + static void dump_regs(const struct superio_registers reg_table[], - int i, int j, uint16_t port, uint8_t ldn_sel) + int i, int j, uint16_t port, uint8_t ldn_sel, + const extra_selector_state_t esel_tbl[], int esel_tbl_size) { int k; const int16_t *idx, *def; + const uint8_t ldn = reg_table[i].ldn[j].ldn; + const char *ldn_name = reg_table[i].ldn[j].name; - if (reg_table[i].ldn[j].ldn != NOLDN) { - printf("LDN 0x%02x", reg_table[i].ldn[j].ldn); - if (reg_table[i].ldn[j].name != NULL) - printf(" (%s)", reg_table[i].ldn[j].name); - regwrite(port, ldn_sel, reg_table[i].ldn[j].ldn); + if (ldn != NOLDN) { + printf("LDN 0x%02x", ldn); + if (ldn_name != NULL) + printf(" (%s)", ldn_name); + regwrite(port, ldn_sel, ldn); } else { - if (reg_table[i].ldn[j].name == NULL) + if (ldn_name == NULL) printf("Register dump:"); else - printf("(%s)", reg_table[i].ldn[j].name); + printf("(%s)", ldn_name); } idx = reg_table[i].ldn[j].idx; @@ -118,6 +143,21 @@ continue; } + if (idx[k] == EXT_SELECTOR) { + const extra_selector_state_t *sel = get_ext_sel_state_entry(esel_tbl, + esel_tbl_size, def[k]); + + printf("=============================\n"); + if (sel == NULL) + printf("[XXXX] XXXX XXXX ESEL[%02d]\n", def[k]); + else + printf("[0x%02x] 0x%02x 0x%02x ESEL[%02d]\n", sel->idx, sel->val, + set_extra_selector(port, sel), def[k]); + printf("=============================\n"); + + continue; + } + printf("0x%02x: ", idx[k]); val = regval(port, idx[k]); @@ -139,6 +179,19 @@ for (k = 0; idx[k] != EOT; k++) { if (k && !(k % 8)) putchar(' '); + + if (idx[k] == EXT_SELECTOR) { + const extra_selector_state_t *sel = get_ext_sel_state_entry(esel_tbl, + esel_tbl_size, def[k]); + + if (sel == NULL) + printf(" [XX]"); + else + printf(" [%02x]", sel->idx); + + continue; + } + printf(" %02x", idx[k]); } @@ -146,6 +199,18 @@ for (k = 0; idx[k] != EOT; k++) { if (k && !(k % 8)) putchar(' '); + + if (idx[k] == EXT_SELECTOR) { + const extra_selector_state_t *sel = get_ext_sel_state_entry(esel_tbl, + esel_tbl_size, def[k]); + + if (sel == NULL) + printf(" [XX]"); + else + printf(" [%02x]", set_extra_selector(port, sel)); + + continue; + } printf(" %02x", regval(port, idx[k])); } @@ -159,16 +224,24 @@ printf(" RR"); else if (def[k] == MISC) printf(" MM"); - else + else if (idx[k] == EXT_SELECTOR) { + const extra_selector_state_t *sel = get_ext_sel_state_entry( + esel_tbl, esel_tbl_size, def[k]); + if (sel == NULL) + printf(" [XX]"); + else + printf(" [%02x]", sel->val); + } else printf(" %02x", def[k]); } } printf("\n"); } -void dump_superio(const char *vendor, +void dump_superio_with_extra_selector(const char *vendor, const struct superio_registers reg_table[], - uint16_t port, uint16_t id, uint8_t ldn_sel) + uint16_t port, uint16_t id, uint8_t ldn_sel, + const extra_selector_state_t esel_tbl[], int esel_tbl_size) { int i, j, no_dump_available = 1; @@ -186,7 +259,7 @@ if (reg_table[i].ldn[j].ldn == EOT) break; no_dump_available = 0; - dump_regs(reg_table, i, j, port, ldn_sel); + dump_regs(reg_table, i, j, port, ldn_sel, esel_tbl, esel_tbl_size); } if (no_dump_available) @@ -194,6 +267,13 @@ } } +void dump_superio(const char *vendor, + const struct superio_registers reg_table[], + uint16_t port, uint16_t id, uint8_t ldn_sel) +{ + dump_superio_with_extra_selector(vendor, reg_table, port, id, ldn_sel, NULL, 0); +} + void dump_io(uint16_t iobase, uint16_t length) { uint16_t i; diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1409030..d60f0a9 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -121,6 +121,9 @@ Used for registers depending on external pin straps configuring static, but board-specific settings like SIO base address or AMD/Intel power seqencing type. */ +#define EXT_SELECTOR -6 /* Defines the operation of setting an extra + specific selector in the configuration register. + Used for fintek chips */ #define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ #define MAXNUMIDX 170 /* Maximum number of indices */ @@ -131,6 +134,14 @@ #define LDN_SEL 0x07 /* LDN select register */ #define WINBOND_HWM_SEL 0x4e /* Hardware monitor bank select */ +/* Structure describing the extra selector and its stat (see fintek.c) */ +typedef struct { + int16_t id; + uint8_t idx; + uint8_t mask; + uint8_t val; +} extra_selector_state_t; + /* Command line parameters. */ extern int dump, verbose, extra_dump; @@ -163,6 +174,10 @@ int superio_unknown(const struct superio_registers reg_table[], uint16_t id); const char *get_superio_name(const struct superio_registers reg_table[], uint16_t id); +void dump_superio_with_extra_selector(const char *vendor, + const struct superio_registers reg_table[], + uint16_t port, uint16_t id, uint8_t ldn_sel, + const extra_selector_state_t esel_tbl[], int esel_tbl_size); void dump_superio(const char *name, const struct superio_registers reg_table[], uint16_t port, uint16_t id, uint8_t ldn_sel); void dump_io(uint16_t iobase, uint16_t length); -- To view, visit https://review.coreboot.org/c/coreboot/+/83196?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If56af9f977381e637245bdd26563f5ba7e6cbead Gerrit-Change-Number: 83196 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

1 0

[M] Change in coreboot[main]: util/superiotool/fintek: Add f81866 register table
by Maxim (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Felix Held, Felix Singer, Maxim, Michał Żygowski. Hello Felix Held, Felix Singer, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83004?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/superiotool/fintek: Add f81866 register table ...................................................................... util/superiotool/fintek: Add f81866 register table In accordance with the F81866A datasheet: Release Date: Jan, 2012, Version: V0.14P [1]. [1] http://www.jetwaycomputer.com/download/Fintek/F81866_wdt_gpio.zip Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 129 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/83004/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/83004?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4367a1129fe628e7bf05d49678ea1c3718da710b Gerrit-Change-Number: 83004 Gerrit-PatchSet: 10 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[M] Change in coreboot[main]: util/superiotool/fintek: Add f81966 register table
by Maxim (Code Review) 24 Jun '24

24 Jun '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83019?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/superiotool/fintek: Add f81966 register table ...................................................................... util/superiotool/fintek: Add f81966 register table In accordance with the F81962/F81964/F81966/F81967 datasheet: Release Date: Feb, 2018, Version: V0.18P [1]. Tested on Asrock IMB-1222 [2]. [1] http://www.jetwaycomputer.com/download/Fintek/F81966_wdt_gpio.zip [2] CB:83107 Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/superiotool/fintek.c 1 file changed, 90 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/83019/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/83019?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic3418c337883538e47eb181cbe1ad2dc828e12a1 Gerrit-Change-Number: 83019 Gerrit-PatchSet: 8 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/83136/comment/ca4c082e_7a11fb19?us… : PS3, Line 146: index++; > Maybe ... I will try another patch and let us review there. The update is at https://review.coreboot.org/c/coreboot/+/82431, could you please review? -- To view, visit https://review.coreboot.org/c/coreboot/+/83136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Gerrit-Change-Number: 83136 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 24 Jun 2024 14:48:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/83136?usp=email ) Change subject: soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83136/comment/41937b17_b080162f?us… : PS3, Line 10: not for PCIe device usage. > Not for DRAM either. It's simply unusable to us, right? I would […] Right, 'is reserved for unknown devices' is a proper wording. Updated. File src/soc/intel/xeon_sp/chip_gen1.c: https://review.coreboot.org/c/coreboot/+/83136/comment/6c2f5e78_858c90bf?us… : PS3, Line 62: (reserved_mmio <= sr->PciResourceMem32Limit)) > Shouldn't align with the if body. i.e. either do […] Done File src/soc/intel/xeon_sp/spr/ioat.c: https://review.coreboot.org/c/coreboot/+/83136/comment/3203bc9b_8466a211?us… : PS3, Line 143: (reserved_mmio <= sr->PciResourceMem32Limit)) { > Same alignment issue. Done https://review.coreboot.org/c/coreboot/+/83136/comment/f950d458_a02b60d5?us… : PS3, Line 146: index++; > This could be handled with an optional pointer argument to create_ioat_domain(), […] Maybe ... I will try another patch and let us review there. -- To view, visit https://review.coreboot.org/c/coreboot/+/83136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8 Gerrit-Change-Number: 83136 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 24 Jun 2024 14:47:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2024