coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/brox/lotso: Add Fn key scancode
by Dengwu Yu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Wen Zhang. Dengwu Yu has posted comments on this change by Wen Zhang. ( https://review.coreboot.org/c/coreboot/+/83204?usp=email ) Change subject: mb/google/brox/lotso: Add Fn key scancode ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Gerrit-Change-Number: 83204 Gerrit-PatchSet: 1 Gerrit-Owner: Wen Zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wen Zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Jun 2024 06:46:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/trulo/var/orisa: Fill in ec.h
by Eric Lai (Code Review) 24 Jun '24

24 Jun '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83154?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/trulo/var/orisa: Fill in ec.h ...................................................................... mb/google/trulo/var/orisa: Fill in ec.h Fill in ec.h according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83154 Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/orisa/include/variant/ec.h 1 file changed, 70 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Derek Huang: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h index 7a2a6ff..877176c 100644 --- a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h +++ b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h @@ -3,6 +3,75 @@ #ifndef __VARIANT_EC_H__ #define __VARIANT_EC_H__ -#include <baseboard/ec.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <variant/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3/S0ix with: + * 1. Lid open + * 2. Power button + * 3. AC Connect/Disconnect + * 4. Key press + * 5. Mode change + * 6. Low battery + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp support */ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/83154?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161 Gerrit-Change-Number: 83154 Gerrit-PatchSet: 5 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/trulo/var/orisa: Fill in gpio.h
by Eric Lai (Code Review) 24 Jun '24

24 Jun '24

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83155?usp=email ) Change subject: mb/google/trulo/var/orisa: Fill in gpio.h ...................................................................... mb/google/trulo/var/orisa: Fill in gpio.h Fill ec pins in gpio.h and configure GPE0 DW2 in overridetree according to schematic_20240614. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83155 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/orisa/include/variant/gpio.h M src/mainboard/google/brya/variants/orisa/overridetree.cb 2 files changed, 13 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Derek Huang: Looks good to me, approved Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h index 0848b4b..c362383 100644 --- a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h @@ -3,9 +3,20 @@ #ifndef VARIANT_GPIO_H #define VARIANT_GPIO_H -#include <baseboard/gpio.h> +#include <soc/gpe.h> +#include <soc/gpio.h> +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI +/* EC wake is EC_SOC_WAKE_ODL which is routed to GPP_F17 */ +#define GPE_EC_WAKE GPE0_DW2_17 /* WP signal to PCH */ #define GPIO_PCH_WP GPP_E3 +/* EC in RW or RO */ +#define GPIO_EC_IN_RW GPP_F18 +/* GPIO IRQ for tight timestamps, MKBP interrupts */ +#define EC_SYNC_IRQ GPD2_IRQ +/* Used to gate SoC's SLP_S0# signal */ +#define GPIO_SLP_S0_GATE GPP_H18 #endif diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 600eb02..832e0c9 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -14,6 +14,7 @@ # GPE configuration register "pmc_gpe0_dw1" = "GPP_B" + register "pmc_gpe0_dw2" = "GPP_F" # S0ix enable register "s0ix_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Gerrit-Change-Number: 83155 Gerrit-PatchSet: 9 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb: source site-local mainboard Kconfig.name and Kconfig files
by David Hendricks (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Alexander Couzens, Evgeny Zinoviev, Felix Held, Felix Singer, Jeremy Soller, Jonathon Hall, Martin L Roth, Matt DeVillier, Michael Niewöhner, Michał Żygowski, Philipp Hug, Piotr Król, Ron Minnich, Sean Rhodes, Tim Crawford. David Hendricks has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/83119?usp=email ) Change subject: mb: source site-local mainboard Kconfig.name and Kconfig files ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: I like this idea, but does it need to be applied broadly? Maybe it's best to keep the added `source` lines where it's most likely needed (silicon vendor mainboard targets, among perhaps a few others) and document the rationale in https://doc.coreboot.org/tutorial/managing_local_additions.html#integration…. OTOH, doing it broadly helps with overall uniformity of the Kconfig files and makes site-local usage a bit more obvious. -- To view, visit https://review.coreboot.org/c/coreboot/+/83119?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4106fea7197c979e6648ebbbbaa107070c916727 Gerrit-Change-Number: 83119 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 25 Jun 2024 06:39:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/trulo/var/orisa: Fill in gpio.h
by Eric Lai (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Amanda Hwang, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/83155?usp=email ) Change subject: mb/google/trulo/var/orisa: Fill in gpio.h ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83155?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9de842a8a66632314d5fdf6444005d34338a1100 Gerrit-Change-Number: 83155 Gerrit-PatchSet: 8 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Jun 2024 06:39:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox/lotso: Add Fn key scancode
by Wen Zhang (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Dengwu Yu. Wen Zhang has posted comments on this change by Wen Zhang. ( https://review.coreboot.org/c/coreboot/+/83204?usp=email ) Change subject: mb/google/brox/lotso: Add Fn key scancode ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/83204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I999627f0ea9db1d79376150a04920ac877a48447 Gerrit-Change-Number: 83204 Gerrit-PatchSet: 1 Gerrit-Owner: Wen Zhang <zhangwen6(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 25 Jun 2024 06:31:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: acpi: Add support for DRHD size reporting
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeff Daly, Jincheng Li, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Nick Vaccaro, Nico Huber, Patrick Rudolph, Paul Menzel, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeff Daly, Jincheng Li, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Nick Vaccaro, Nico Huber, Patrick Rudolph, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82429?usp=email to look at the new patch set (#16). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: acpi: Add support for DRHD size reporting ...................................................................... acpi: Add support for DRHD size reporting VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpi_dmar.c M src/include/acpi/acpi.h 2 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/82429/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/82429?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49dd5de2eca257a5f6240e36d05755cabca96d1c Gerrit-Change-Number: 82429 Gerrit-PatchSet: 16 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/common/block: Add vtd_probe_bar_size
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Shuo Liu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/82430?usp=email ) Change subject: soc/intel/common/block: Add vtd_probe_bar_size ...................................................................... Abandoned Abandon this one as of now due to we are moving ahead in another thread. -- To view, visit https://review.coreboot.org/c/coreboot/+/82430?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfa5d6cd6889035cd3ebbec5028eca2e92178c6b Gerrit-Change-Number: 82430 Gerrit-PatchSet: 19 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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[S] Change in coreboot[main]: acpi: Add support for DRHD size reporting
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Chen, Gang C, Cliff Huang, Jincheng Li, Lance Zhao, Tim Wawrzynczak. Hello Chen, Gang C, Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/83203?usp=email to review the following change. Change subject: acpi: Add support for DRHD size reporting ...................................................................... acpi: Add support for DRHD size reporting VT-d spec 4.0 supports size definition for DRHD BAR to support DRHD sizes larger than 4KB. If the value in the field is N, the size of the register set is 2^N 4 KB pages. Some latest OS (e.g. Linux kernel 6.5) will have VTd driver trying to use the beyond 4KB part of the DRHD BAR if they exist. They need the DRHD size field to set up page mapping before access those registers. Re-add acpi_create_dmar_drhd with a size parameter to support the needs. TEST=Build and boot on intel/archercity CRB Change-Id: I8749b96325807960a1859a39f6348d227b040970 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpi_dmar.c M src/include/acpi/acpi.h 2 files changed, 23 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/83203/1 diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 20a100d..b5c8efc 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -2,7 +2,9 @@ #include <acpi/acpi.h> #include <arch/ioapic.h> +#include <assert.h> #include <cpu/cpu.h> +#include <lib.h> #include <version.h> void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, @@ -39,6 +41,12 @@ unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar) { + return acpi_create_dmar_drhd(current, flags, segment, bar, 1); +} + +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u64 bar, u32 size) +{ dmar_entry_t *drhd = (dmar_entry_t *)current; memset(drhd, 0, sizeof(*drhd)); drhd->type = DMAR_DRHD; @@ -46,6 +54,18 @@ drhd->flags = flags; drhd->segment = segment; drhd->bar = bar; + drhd->size = log2(size) - 12; + + /* + * Refer to chapter 8.3 of https://cdrdv2.intel.com/v1/dl/getContent/671081 + * max 2^15 pages, 4 KiB each. + */ + assert(size <= (1 << 15) * (4 * KiB)); + /* + * drhd->bar must be aligned according to the size of the register set size + * reported in the drhd->size. + */ + assert(!(drhd->bar & ((1 << (drhd->size + 12)) - 1))); return drhd->length; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 469d672..77c1ec6 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -638,7 +638,7 @@ u16 type; u16 length; u8 flags; - u8 reserved; + u8 size; u16 segment; u64 bar; } __packed dmar_entry_t; @@ -1851,6 +1851,8 @@ unsigned long (*acpi_fill_dmar)(unsigned long)); unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar); +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, + u16 segment, u64 bar, u32 size); unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, -- To view, visit https://review.coreboot.org/c/coreboot/+/83203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8749b96325807960a1859a39f6348d227b040970 Gerrit-Change-Number: 83203 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

1 0

[M] Change in coreboot[main]: acpi: Rename acpi_create_dmar_drhd
by Shuo Liu (Code Review) 24 Jun '24

24 Jun '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jeff Daly, Johnny Lin, Jonathan Zhang, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Nick Vaccaro, Patrick Rudolph, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Vanessa Eusebio, Werner Zeh. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83202?usp=email ) Change subject: acpi: Rename acpi_create_dmar_drhd ...................................................................... acpi: Rename acpi_create_dmar_drhd For most of SoCs, DRHD is by default with the size of 4KB. However, larger sizes are allowed as well. Rename acpi_create_dmar_drhd to acpi_create_dmar_drhd_4k to support the default case while a later patch will re-add acpi_create_dmar_drhd with a size parameter. TEST=intel/archercity CRB Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpi_dmar.c M src/include/acpi/acpi.h M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c M src/soc/intel/xeon_sp/uncore_acpi.c 16 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83202/1 diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 3853142..20a100d 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -36,7 +36,7 @@ header->checksum = acpi_checksum((void *)dmar, header->length); } -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, +unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar) { dmar_entry_t *drhd = (dmar_entry_t *)current; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 4a71aef..469d672 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1849,7 +1849,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, unsigned long (*acpi_fill_dmar)(unsigned long)); -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, +unsigned long acpi_create_dmar_drhd_4k(unsigned long current, u8 flags, u16 segment, u64 bar); unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit); diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index 246fe9a..70f0736 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -25,13 +25,13 @@ PCI_CLASS_REVISION); unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE1); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE1); current += acpi_create_dmar_ds_pci(current, 0, 0x1b, 0); acpi_dmar_drhd_fixup(tmp, current); if (stepping != STEPPING_B2 && igd_active) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE2); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE2); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x2, 1); acpi_dmar_drhd_fixup(tmp, current); @@ -39,7 +39,7 @@ if (me_active) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, IOMMU_BASE3); + current += acpi_create_dmar_drhd_4k(current, 0, 0, IOMMU_BASE3); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 0); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 1); current += acpi_create_dmar_ds_pci(current, 0, 0x3, 2); @@ -47,7 +47,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, IOMMU_BASE4); /* TODO: reserve GTT for 0.2.0 and 0.2.1? */ return current; diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index f3c107b..bd2f719 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -28,7 +28,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -37,7 +37,7 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 8be161e..3ffab4d 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -34,14 +34,14 @@ if (igfx && igfx->enabled) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, GFXVT_BASE); + current += acpi_create_dmar_drhd_4k(current, 0, 0, GFXVT_BASE); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 7687f02..dcf8a7c 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -239,7 +239,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -251,7 +251,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -265,7 +265,7 @@ if (tbtbar && tbten) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar); current += acpi_create_dmar_ds_pci_br(current, 0, SA_DEV_SLOT_TBT, i); @@ -280,7 +280,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index b84e454..c9f76eb 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -126,7 +126,7 @@ if (emit_igd) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); } @@ -138,7 +138,7 @@ union p2sb_bdf hbdf = p2sb_get_hpet_bdf(); p2sb_hide(); - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 3fe574f..4c1cdf3 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -38,7 +38,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -47,7 +47,7 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index a58c4f0..1fd16e9 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -261,7 +261,7 @@ if (emit_igd) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -273,7 +273,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, 5, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -285,7 +285,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..afda045 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -173,7 +173,7 @@ if (!vtbar) return current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtbar); current += acpi_create_dmar_ds_ioapic_from_hw(current, diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index f566ce5..8e9c9be 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -175,7 +175,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -187,7 +187,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 6cf7ef5..5e432a9 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -173,7 +173,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -185,7 +185,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, 5, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -197,7 +197,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index c8d1978..a3ee198 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -235,14 +235,14 @@ __func__, gfxvtbar, MCHBAR32(GFXVTBAR)); if (is_devfn_enabled(PCI_DEVFN_IGD) && gfxvtbar && gfxvten) { tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, PCI_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); } tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 6a56071..e0381e8 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -193,7 +193,7 @@ if (emit_igd) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfx_vtbar); current += acpi_create_dmar_ds_pci(current, 0, 2, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -206,7 +206,7 @@ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_IBDF_BUS, V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 5c4c838..c34b185 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -232,7 +232,7 @@ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, gfxvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IGD, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -244,7 +244,7 @@ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, ipuvtbar); current += acpi_create_dmar_ds_pci(current, 0, SA_DEV_SLOT_IPU, 0); acpi_dmar_drhd_fixup(tmp, current); @@ -257,7 +257,7 @@ if (tbtbar && tbten) { unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, 0, 0, tbtbar); + current += acpi_create_dmar_drhd_4k(current, 0, 0, tbtbar); current += acpi_create_dmar_ds_pci_br(current, 0, SA_DEV_SLOT_TBT, i); @@ -271,7 +271,7 @@ if (vtvc0bar && vtvc0en) { const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 6b6363d..a0bbbff 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -272,12 +272,12 @@ printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base); } // Add PCH IOAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/83202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic0a0618aa8e46d3fec2ceac7a91742122993df91 Gerrit-Change-Number: 83202 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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coreboot-gerrit June 2024