coreboot-gerrit June 2024

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[M] Change in coreboot[main]: mb/system76: Add SPDX ID to devicetree files
by Felix Held (Code Review) 03 Jun '24

03 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82700?usp=email ) Change subject: mb/system76: Add SPDX ID to devicetree files ...................................................................... mb/system76: Add SPDX ID to devicetree files Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82700 Reviewed-by: Jeremy Soller <jeremy(a)system76.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/system76/addw1/devicetree.cb M src/mainboard/system76/addw1/variants/addw1/overridetree.cb M src/mainboard/system76/addw1/variants/addw2/overridetree.cb M src/mainboard/system76/adl/devicetree.cb M src/mainboard/system76/adl/variants/darp8/overridetree.cb M src/mainboard/system76/adl/variants/galp6/overridetree.cb M src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb M src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb M src/mainboard/system76/adl/variants/lemp11/overridetree.cb M src/mainboard/system76/adl/variants/oryp10/overridetree.cb M src/mainboard/system76/adl/variants/oryp9/overridetree.cb M src/mainboard/system76/bonw14/devicetree.cb M src/mainboard/system76/cml-u/devicetree.cb M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb M src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb M src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb M src/mainboard/system76/kbl-u/devicetree.cb M src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb M src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb M src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb M src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb M src/mainboard/system76/rpl/devicetree.cb M src/mainboard/system76/rpl/variants/addw3/overridetree.cb M src/mainboard/system76/rpl/variants/bonw15/overridetree.cb M src/mainboard/system76/rpl/variants/darp9/overridetree.cb M src/mainboard/system76/rpl/variants/galp7/overridetree.cb M src/mainboard/system76/rpl/variants/gaze18/overridetree.cb M src/mainboard/system76/rpl/variants/lemp12/overridetree.cb M src/mainboard/system76/rpl/variants/oryp11/overridetree.cb M src/mainboard/system76/rpl/variants/serw13/overridetree.cb M src/mainboard/system76/tgl-h/devicetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb M src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb M src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb M src/mainboard/system76/tgl-u/devicetree.cb M src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb M src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb M src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/mainboard/system76/whl-u/variants/darp5/overridetree.cb M src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb 47 files changed, 94 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c..16827ddb 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb index fa327fd..b1fab29 100644 --- a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb index 40e2128..3b9c562 100644 --- a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 9a78415..9a7a149 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 73d016f..7a7e14e 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb index a0a0ad2..79c614e 100644 --- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 960ead6..603879b 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index 74b87ee..a9c614e4 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb index 1e65248..10c6bfcf 100644 --- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index efebe7a..09f07b6 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index 2f79c9e..4ca81ab 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa76..aa7d1ab 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 90c5b71..07c56b4 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ /* Touchpad */ diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index b349762..17b1ba1 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1404 inherit diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index bbfc2ea..9c747cf 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1403 inherit diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 164774a..2279cb3 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d..f80c45c 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb index 0cfd040..e94d703 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb index 9f64b5f..02275df 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 3b84d7f..da3327a 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb index 9e042a3..8fb495b 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1303 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb index 134fbec..5cc90b26 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1413 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb index 8a61f28..d18dfa4 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1313 inherit diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f..ae52165 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a..abf68b9 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb index 3d6355e..3b2748f 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x50d3 inherit diff --git a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb index 3be1b15..b9bb816 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x65e5 inherit diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index 4fd50fd..749ce53 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb index 9b8d453..24c272c 100644 --- a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb index fde40f6..a1191a5 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index fc9b49a..3dc2786 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, diff --git a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb index 0c0aec3..cc060e4 100644 --- a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb index 4c11595..636d57c 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x5630 inherit diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb index 34950cc..c84628b 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb index d337a57..57bc594 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x66a2 inherit diff --git a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb index b261d59..cc89764 100644 --- a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 353a96d..11b85ce 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index ad90eab..6ac474d 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x5015 inherit diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index bfbc5c5..b4b62fa 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x50e1 inherit diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index a09cf30..0967154 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index f056da7..ae80a32 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index a35dc52..b263c5a 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 075a2e4..7cfc62b 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index ce45079..a4e3052 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 0899f62..6607f45 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Lock Down register "common_soc_config" = "{ diff --git a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb index b9c9de7..c72111a 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1325 inherit diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb index 022be95..4556940 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1323 inherit -- To view, visit https://review.coreboot.org/c/coreboot/+/82700?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Gerrit-Change-Number: 82700 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
by Felix Held (Code Review) 03 Jun '24

03 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82685?usp=email ) Change subject: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree ...................................................................... soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this to 1 is needed to enable HDA audio link. Same exact situation as with Alder Lake in CL 71715. Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82685 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/fsp_params.c 2 files changed, 2 insertions(+), 7 deletions(-) Approvals: Tim Crawford: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 0c76b7c..7168369 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -247,6 +247,7 @@ uint16_t sata_ports_dito_val[8]; /* Audio related */ + uint8_t pch_hda_audio_link_hda_enable; uint8_t pch_hda_dsp_enable; bool pch_hda_sdi_enable[MAX_HD_AUDIO_SDI_LINKS]; diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 0f44d65..ec0bb8d 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -288,17 +288,11 @@ m_cfg->PchHdaIDispLinkTmode = config->pch_hda_idisp_link_tmode; m_cfg->PchHdaIDispLinkFrequency = config->pch_hda_idisp_link_frequency; m_cfg->PchHdaIDispCodecDisconnect = !config->pch_hda_idisp_codec_enable; + m_cfg->PchHdaAudioLinkHdaEnable = config->pch_hda_audio_link_hda_enable; for (int i = 0; i < MAX_HD_AUDIO_SDI_LINKS; i++) m_cfg->PchHdaSdiEnable[i] = config->pch_hda_sdi_enable[i]; - /* - * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to - * configure GPIO pads for audio. Mainboard is expected to perform all GPIO - * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO - * configuration for audio pads. - */ - m_cfg->PchHdaAudioLinkHdaEnable = 0; memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); -- To view, visit https://review.coreboot.org/c/coreboot/+/82685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Gerrit-Change-Number: 82685 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[XL] Change in coreboot[main]: ec/dasharo/ec: Add initial copy of ec/system76/ec
by Felix Held (Code Review) 03 Jun '24

03 Jun '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82671?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: ec/dasharo/ec: Add initial copy of ec/system76/ec ...................................................................... ec/dasharo/ec: Add initial copy of ec/system76/ec Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit 0a280ff7) with string changes. Dasharo-specific features will be added in subsequent commits, similar to how Librem EC support was added in changes 52390 and 52391. Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82671 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- A src/ec/dasharo/ec/Kconfig A src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi/ac.asl A src/ec/dasharo/ec/acpi/battery.asl A src/ec/dasharo/ec/acpi/battery_thresholds.asl A src/ec/dasharo/ec/acpi/buttons.asl A src/ec/dasharo/ec/acpi/ec.asl A src/ec/dasharo/ec/acpi/ec_ram.asl A src/ec/dasharo/ec/acpi/hid.asl A src/ec/dasharo/ec/acpi/lid.asl A src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/dasharo_ec.c A src/ec/dasharo/ec/dasharo_ec.h A src/ec/dasharo/ec/smbios.c 14 files changed, 1,045 insertions(+), 0 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig new file mode 100644 index 0000000..1a007fa --- /dev/null +++ b/src/ec/dasharo/ec/Kconfig @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_DASHARO_EC + bool + help + Dasharo EC + +config EC_DASHARO_EC_BAT_THRESHOLDS + depends on EC_DASHARO_EC + bool + default y + +config EC_DASHARO_EC_DGPU + depends on EC_DASHARO_EC + bool + default n + +config EC_DASHARO_EC_OLED + depends on EC_DASHARO_EC + bool + default n diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk new file mode 100644 index 0000000..247bcd4 --- /dev/null +++ b/src/ec/dasharo/ec/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_EC_DASHARO_EC),y) + +all-y += dasharo_ec.c + +ramstage-y += smbios.c + +smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c + +endif diff --git a/src/ec/dasharo/ec/acpi/ac.asl b/src/ec/dasharo/ec/acpi/ac.asl new file mode 100644 index 0000000..66cf742 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, 1) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/ec/dasharo/ec/acpi/battery.asl b/src/ec/dasharo/ec/acpi/battery.asl new file mode 100644 index 0000000..106f3d1 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/battery.asl @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) + Name (_UID, 0) + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, 0) + Method (_STA, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + 1, // 0 - Power Unit + 0xFFFFFFFF, // 1 - Design Capacity + 0xFFFFFFFF, // 2 - Last Full Charge Capacity + 1, // 3 - Battery Technology + 0xFFFFFFFF, // 4 - Design Voltage + 0, // 5 - Design Capacity of Warning + 0, // 6 - Design Capacity of Low + 0x40, // 7 - Battery Capacity Granularity 1 + 0x40, // 8 - Battery Capacity Granularity 2 + " ", // 9 - Model Number + " ", // 10 - Serial Number + " ", // 11 - Battery Type + " " // 12 - OEM Information + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [2] = 0xFFFFFFFF + PBIF [4] = 0xFFFFFFFF + PBIF [9] = " " + PBIF [10] = " " + PBIF [11] = " " + PBIF [12] = " " + BFCC = 0 + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [1] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [2] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [4] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [5] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [6] = Local0 + PBIF [9] = "BAT" + PBIF [10] = "0001" + PBIF [11] = "LION" + PBIF [12] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBIX, Package () + { + 0, // 0 - Revision + 1, // 1 - Power Unit: mAh + 0xFFFFFFFF, // 2 - Design Capacity + 0xFFFFFFFF, // 3 - Last Full Charge Capacity + 1, // 4 - Battery Technology: Rechargeable + 0xFFFFFFFF, // 5 - Design Voltage + 0, // 6 - Design Capacity of Warning + 0, // 7 - Design Capacity of Low + 0, // 8 - Cycle Count + 98000, // 9 - Measurement Accuracy + 0xFFFFFFFF, // 10 - Max Sampling Time + 0xFFFFFFFF, // 11 - Min Sampling Time + 0xFFFFFFFF, // 12 - Max Averaging Interval + 0xFFFFFFFF, // 13 - Min Averaging Interval + 0x40, // 14 - Battery Capacity Granularity 1 + 0x40, // 15 - Battery Capacity Granularity 2 + " ", // 16 - Model Number + " ", // 17 - Serial Number + " ", // 18 - Battery Type + " " // 19 - OEM Information + }) + + Method (IVBX, 0, NotSerialized) + { + PBIX [2] = 0xFFFFFFFF + PBIX [3] = 0xFFFFFFFF + PBIX [5] = 0xFFFFFFFF + PBIX [16] = " " + PBIX [17] = " " + PBIX [18] = " " + PBIX [19] = " " + BFCC = 0 + } + + Method (UPBX, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIX [2] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIX [3] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIX [5] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIX [6] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIX [7] = Local0 + LOCAL0 = ^^PCI0.LPCB.EC0.CYC0 + PBIX [8] = LOCAL0 + PBIX [16] = "BAT" + PBIX [17] = "0001" + PBIX [18] = "LION" + PBIX [19] = "Notebook" + } + Else + { + IVBX () + } + } + + // _BIX: Battery Information Extended + Method (_BIX, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBX () + } + Else + { + IVBX () + } + Return (PBIX) /* \_SB_.BAT0.PBIX */ + } + + Name (PBST, Package (0x04) + { + 0, // 0 - Battery state + 0xFFFFFFFF, // 1 - Battery present rate + 0xFFFFFFFF, // 2 - Battery remaining capacity + 0xFFFFFFFF // 3 - Battery present voltage + }) + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [2] = 0xFFFFFFFF + PBST [3] = 0xFFFFFFFF + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = 0 + Local1 = 0 + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= 1 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [0] = Local0 + PBST [1] = Local1 + PBST [2] = Local2 + PBST [3] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/ec/dasharo/ec/acpi/battery_thresholds.asl b/src/ec/dasharo/ec/acpi/battery_thresholds.asl new file mode 100644 index 0000000..3bb1330 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/battery_thresholds.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Field (ERAM, ByteAcc, Lock, Preserve) +{ + Offset (0xBC), + BTL0, 8, /* BAT0 charging start threshold */ + BTH0, 8, /* BAT0 charging end threshold */ +} + +/* + * Get battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + */ +Method (GBCT, 1, NotSerialized) +{ + If (Arg0 == 0) { + Return (BTL0) + } + + If (Arg0 == 1) { + Return (BTH0) + } + + Return (0xFF) +} + +/* + * Set battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + * Arg1: Percentage + */ +Method (SBCT, 2, NotSerialized) +{ + If (Arg1 <= 100) { + If (Arg0 == 0) { + BTL0 = Arg1 + } + If (Arg0 == 1) { + BTH0 = Arg1 + } + } +} diff --git a/src/ec/dasharo/ec/acpi/buttons.asl b/src/ec/dasharo/ec/acpi/buttons.asl new file mode 100644 index 0000000..ae85c67 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/buttons.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl new file mode 100644 index 0000000..e4fcdeb --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" +} + +Device (\_SB.PCI0.LPCB.EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) + Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "ec_ram.asl" + + Name (ECOK, 0) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1)) + If ((Arg0 == 0x03) && (Arg1 == 1)) { + // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + ECOS = 1 + + // Enable software display brightness keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, 0) + Notify(^^^^BAT0, 0) + + PNOT () + + // EC is now available + ECOK = Arg1 + + // Reset Dasharo Device + ^^^^S76D.RSET() + } + } + + Name (S3OS, 0) + Method (PTS, 1, Serialized) { + Printf ("EC: PTS: %o", ToHexString(Arg0)) + If (ECOK) { + // Save ECOS during sleep + S3OS = ECOS + + // Clear wake cause + WFNO = 0 + } + } + + Method (WAK, 1, Serialized) { + Printf ("EC: WAK: %o", ToHexString(Arg0)) + If (ECOK) { + // Restore ECOS after sleep + ECOS = S3OS + + // Set current AC state + ^^^^AC.ACFG = ADP + + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, 0) + Notify(^^^^BAT0, 0) + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Printf ("EC: Touchpad Toggle") + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Printf ("EC: Screen Toggle") +#if CONFIG(EC_DASHARO_EC_OLED) + Notify (^^^^S76D, 0x85) +#endif // CONFIG(EC_DASHARO_EC_OLED) + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Printf ("EC: Mute") + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Printf ("EC: Keyboard Backlight") + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Printf ("EC: Volume Down") + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Printf ("EC: Volume Up") + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Printf ("EC: Switch Video Mode") + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Printf ("EC: Brightness Down") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (20) + } + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Printf ("EC: Brightness Up") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (19) + } + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Printf ("EC: Camera Toggle") + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Printf ("EC: Airplane Mode") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (8) + } + // TODO: hardware airplane mode + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Printf ("EC: Suspend Button") + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Printf ("EC: AC Detect") + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Notify (^^^^BAT0, 0x80) // Status Change + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Printf ("EC: BAT0 Update (17)") + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Printf ("EC: BAT0 Update (19)") + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Printf ("EC: Lid Close") + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Printf ("EC: Thermal Trip") + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Printf ("EC: Power Button") + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Printf ("EC: White Keyboard Backlight") + Notify (^^^^S76D, 0x80) + } ElseIf (Local0 == 0x9F) { + Printf ("EC: Color Keyboard Toggle") + Notify (^^^^S76D, 0x81) + } ElseIf (Local0 == 0x81) { + Printf ("EC: Color Keyboard Down") + Notify (^^^^S76D, 0x82) + } ElseIf (Local0 == 0x82) { + Printf ("EC: Color Keyboard Up") + Notify (^^^^S76D, 0x83) + } ElseIf (Local0 == 0x80) { + Printf ("EC: Color Keyboard Color Change") + Notify (^^^^S76D, 0x84) + } Else { + Printf ("EC: Other: %o", ToHexString(Local0)) + } + } + + #if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS) + #include "battery_thresholds.asl" + #endif +} diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl new file mode 100644 index 0000000..cb5bcf1 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + Offset (0x03), + LSTE, 1, // Lid is open + , 1, + LWKE, 1, // Lid wake + , 5, + Offset (0x07), + TMP1, 8, // CPU temperature + Offset (0x10), + ADP, 1, // AC adapter connected + , 1, + BAT0, 1, // Battery connected + , 5, + WFNO, 8, // Wake cause (not implemented) + Offset (0x16), + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity + Offset (0x22), + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage + Offset (0x3A), + BCW0, 32, + BCL0, 32, + CYC0, 16, // Battery cycle count + Offset (0x68), + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + Offset (0xC8), + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data + Offset (0xCD), + TMP2, 8, // GPU temperature + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM + Offset (0xD9), + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, +} diff --git a/src/ec/dasharo/ec/acpi/hid.asl b/src/ec/dasharo/ec/acpi/hid.asl new file mode 100644 index 0000000..eb5f420 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/hid.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, 0) + Name (HIDX, 0) + Name (HRDY, 0) + + Method (HDEM, 0, Serialized) + { + HBSY = 0 + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (0) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = 1 + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = 0 + While ((Local0 < 0xFA) && HBSY) + { + Sleep (0x04) + Local0++ + } + + If (HBSY == 1) + { + HBSY = 0 + HIDX = 0 + Return (1) + } + Else + { + Return (0) + } + } +} diff --git a/src/ec/dasharo/ec/acpi/lid.asl b/src/ec/dasharo/ec/acpi/lid.asl new file mode 100644 index 0000000..0a64341 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/lid.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) + + Method (_LID, 0, NotSerialized) { + Printf ("LID: _LID") + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (1) + } + } + + Method (_PSW, 1, NotSerialized) { + Printf ("LID: _PSW: %o", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/ec/dasharo/ec/acpi/s76.asl b/src/ec/dasharo/ec/acpi/s76.asl new file mode 100644 index 0000000..f23f857 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/s76.asl @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +// 0x85 - OLED screen toggle +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + Method (RSET, 0, Serialized) { + Printf ("S76D: RSET") + SAPL(0) + SKBB(0) + SKBC(0xFFFFFF) + } + + Method (INIT, 0, Serialized) { + Printf ("S76D: INIT") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Printf ("S76D: FINI") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + + // Get Keyboard Backlight Kind + // 0 - No backlight + // 1 - White backlight + // 2 - RGB backlight + Method (GKBK, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 2 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + } + Return (Local0) + } + + // Get Keyboard Brightness + Method (GKBB, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 1 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + } + Return (Local0) + } + + // Set Keyboard Brightness + Method (SKBB, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 0 + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Get Keyboard Color + Method (GKBC, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 4 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16 + Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8 + } + Return (Local0) + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 3 + ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) + ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) + ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU fan", +#endif + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + Local0 = 0 + Local1 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.DUT1 + Local1 = ^^PCI0.LPCB.EC0.RPM1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.DUT2 + Local1 = ^^PCI0.LPCB.EC0.RPM2 + } + } + If (Local1 != 0) { + // 60 * (EC frequency / 120) / 2 + Local1 = 2156250 / Local1 + } + Return ((Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU temp", +#endif + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + Local0 = 0; + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.TMP1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.TMP2 + } + } + Return (Local0) + } +} diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c new file mode 100644 index 0000000..97c9613 --- /dev/null +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "dasharo_ec.h" +#include <arch/io.h> +#include <console/dasharo_ec.h> +#include <console/console.h> +#include <timer.h> + +// This is the command region for Dasharo EC firmware. It must be +// enabled for LPC in the mainboard. +#define DASHARO_EC_BASE 0x0E00 +#define DASHARO_EC_SIZE 256 + +#define REG_CMD 0 +#define REG_RESULT 1 +#define REG_DATA 2 // Start of command data + +// When command register is 0, command is complete +#define CMD_FINISHED 0 + +#define RESULT_OK 0 + +// Print command. Registers are unique for each command +#define CMD_PRINT 4 +#define CMD_PRINT_REG_FLAGS 2 +#define CMD_PRINT_REG_LEN 3 +#define CMD_PRINT_REG_DATA 4 + +static inline uint8_t dasharo_ec_read(uint8_t addr) +{ + return inb(DASHARO_EC_BASE + (uint16_t)addr); +} + +static inline void dasharo_ec_write(uint8_t addr, uint8_t data) +{ + outb(data, DASHARO_EC_BASE + (uint16_t)addr); +} + +void dasharo_ec_init(void) +{ + // Clear entire command region + for (int i = 0; i < DASHARO_EC_SIZE; i++) + dasharo_ec_write((uint8_t)i, 0); +} + +void dasharo_ec_flush(void) +{ + dasharo_ec_write(REG_CMD, CMD_PRINT); + + // Wait for command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + dasharo_ec_write(CMD_PRINT_REG_LEN, 0); +} + +void dasharo_ec_print(uint8_t byte) +{ + uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN); + dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte); + dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1); + + // If we hit the end of the buffer, or were given a newline, flush + if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA)) + dasharo_ec_flush(); +} + +bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, + uint8_t request_size, uint8_t *reply_data, uint8_t reply_size) +{ + if (request_size > DASHARO_EC_SIZE - REG_DATA || + reply_size > DASHARO_EC_SIZE - REG_DATA) { + printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n", + cmd, request_size, reply_size); + return false; + } + + /* If any data were buffered by dasharo_ec_print(), flush it first */ + uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN); + if (buffered_len > 0) + dasharo_ec_flush(); + + /* Write the data */ + uint8_t i; + for (i = 0; i < request_size; ++i) + dasharo_ec_write(REG_DATA + i, request_data[i]); + + /* Write the command */ + dasharo_ec_write(REG_CMD, cmd); + + /* Wait for the command to complete */ + bool ret = true; + int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + if (elapsed == 0) { + /* Timed out: fail the command, don't attempt to read a reply. */ + printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n", + cmd, request_size, reply_size); + ret = false; + } else { + /* Read the reply */ + for (i = 0; i < reply_size; ++i) + reply_data[i] = dasharo_ec_read(REG_DATA+i); + /* Check the reply status */ + ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK); + } + + /* Reset the flags and length so we can buffer console prints again */ + dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0); + dasharo_ec_write(CMD_PRINT_REG_LEN, 0); + + return ret; +} diff --git a/src/ec/dasharo/ec/dasharo_ec.h b/src/ec/dasharo/ec/dasharo_ec.h new file mode 100644 index 0000000..f313b0d --- /dev/null +++ b/src/ec/dasharo/ec/dasharo_ec.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DASHARO_EC_H +#define DASHARO_EC_H + +#include <stdbool.h> +#include <stdint.h> + +/* + * Send a command to the EC. request_data/request_size are the request payload, + * request_data can be NULL if request_size is 0. reply_data/reply_size are + * the reply payload, reply_data can be NULL if reply_size is 0. + */ +bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, + uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); + +#endif diff --git a/src/ec/dasharo/ec/smbios.c b/src/ec/dasharo/ec/smbios.c new file mode 100644 index 0000000..e55d5f0 --- /dev/null +++ b/src/ec/dasharo/ec/smbios.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + // TODO: Read wake source from EC. + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Gerrit-Change-Number: 82671 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

1 0

[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Subrata Banik (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Angel Pons, Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe. Subrata Banik has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/b89b6aef_4a0f3908?us… : PS10, Line 205: & > > > What if the address is below 4G (the high dword is zero, but the low dword is non-zero)? Is this a valid value? > > > > do you mean above 4G? where MSB is non-zero and LSB is zero ? > > I mean MSB is zero and LSB is non-zero, but the scenario you suggested is also a problem with this check. > > This is how I would implement the check: > > ```suggestion > if (!dw1 && !dw0) { > ``` i agree with you. -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 16:19:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Alexander Couzens, Maciej Pijanowski, Paul Menzel. Angel Pons has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ...................................................................... Patch Set 7: (1 comment) File src/mainboard/lenovo/m920q/devicetree.cb: https://review.coreboot.org/c/coreboot/+/80609/comment/9b0247b6_6d502631?us… : PS7, Line 57: : # not populated on M920q. Appears to be populated on M920x : # variant but it was not tested in any way so far. : : device ref pcie_rp21 on # M.2 SSD #1 : register "PcieRpSlotImplemented[20]" = "1" : register "PcieRpEnable[20]" = "1" : register "PcieClkSrcUsage[4]" = "20" : register "PcieClkSrcClkReq[4]" = "4" : end : : device ref pcie_rp9 on # WLAN : register "PcieRpSlotImplemented[8]" = "1" : register "PcieRpEnable[5]" = "1" : register "PcieClkSrcUsage[3]" = "5" : register "PcieClkSrcClkReq[3]" = "3" : end I'm not sure where this info comes from, but it doesn't match the schematics I have. Also, WLAN (`device ref pcie_rp9`) is enabling PCIe RP #6, which is wrong... ```suggestion device ref pcie_rp6 on # WLAN register "PcieRpEnable[5]" = "1" register "PcieRpSlotImplemented[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" end device ref pcie_rp9 on # PCIe x4 register "PcieRpEnable[8]" = "1" register "PcieRpSlotImplemented[8]" = "1" register "PcieClkSrcUsage[2]" = "8" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp17 on # M.2 SSD #2 register "PcieRpEnable[16]" = "1" register "PcieRpSlotImplemented[16]" = "1" register "PcieClkSrcUsage[10]" = "16" register "PcieClkSrcClkReq[10]" = "10" end device ref pcie_rp21 on # M.2 SSD #1 register "PcieRpEnable[20]" = "1" register "PcieRpSlotImplemented[20]" = "1" register "PcieClkSrcUsage[4]" = "20" register "PcieClkSrcClkReq[4]" = "4" end ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Mon, 03 Jun 2024 16:05:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Karthik Ramasubramanian (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Eric Lai, Jian Tong, Kun Liu, Paul Menzel, Shelley Chen, Wentao Qin. Karthik Ramasubramanian has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/82573?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... Patch Set 16: (1 comment) File src/mainboard/google/brox/variants/lotso/gpio.c: https://review.coreboot.org/c/coreboot/+/82573/comment/60e0dad6_78c99cda?us… : PS16, Line 37: LOCK_CONFIG Should we use the LOCK variant only from RO such that RW cannot overwrite the pad config? If so then here we are using it from RW. Or is the intentions to lock the config such that OS cannot overwrite it? -- To view, visit https://review.coreboot.org/c/coreboot/+/82573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Gerrit-Change-Number: 82573 Gerrit-PatchSet: 16 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dengwu Yu <yudengwu(a)huaqin.corp-partner.google.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 15:53:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

1 0

[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Lean Sheng Tan (Code Review) 03 Jun '24

03 Jun '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80322?usp=email ) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... device_tree: Add function to get top of memory from a FDT blob coreboot needs to figure out top of memory to place CBMEM data. On some non-x86 QEMU virtual machines, this is achieved by probing the RAM space to find where the VM starts discarding data since it's not backed by actual RAM. This behaviour seems to have changed on the QEMU side since then, VMs using the "virt" model have started raising exceptions/errors instead of silently discarding data (likely [1] for example) which has previously broken coreboot on these emulation boards. The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models and had this issue, which were mostly fixed by using exception handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing to 16383 MiB because it can run into MMIO regions otherwise. The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which doesn't appear to suffer from this issue. Still, the issue can be observed on the ARMv7 "virt" model via a port based on qemu-aarch64. QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device tree blob it provides for device information (incl. RAM size). Implement functions that parse the device tree blob to find described memory regions and calculate the top of memory in order to use it in mainboard code as an alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't available, so take care to do parsing without unflattening the blob and make the code available in romstage as well. [1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.… [2] https://review.coreboot.org/c/coreboot/+/34774 [3] https://review.coreboot.org/c/coreboot/+/36486 [4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html [5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80322 Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/device_tree.h M src/lib/Makefile.mk M src/lib/device_tree.c 3 files changed, 102 insertions(+), 1 deletion(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified Maximilian Brune: Looks good to me, approved diff --git a/src/include/device_tree.h b/src/include/device_tree.h index 6d2d656..bb522bf 100644 --- a/src/include/device_tree.h +++ b/src/include/device_tree.h @@ -129,6 +129,12 @@ */ int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name); + /* Read memory regions from a flat device-tree. */ +size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[], + size_t regions_count); + /* Find top of memory from a flat device-tree. */ +uint64_t fdt_get_memory_top(const void *blob); + /* Read a flattened device tree into a hierarchical structure which refers to the contents of the flattened tree in place. Modifying the flat tree invalidates the unflattened one. */ diff --git a/src/lib/Makefile.mk b/src/lib/Makefile.mk index e22fd08..59e2116 100644 --- a/src/lib/Makefile.mk +++ b/src/lib/Makefile.mk @@ -160,10 +160,12 @@ ramstage-$(CONFIG_GENERIC_UDELAY) += timer.c ramstage-y += b64_decode.c ramstage-$(CONFIG_ACPI_NHLT) += nhlt.c -ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit.c ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c +romstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c +ramstage-$(CONFIG_FLATTENED_DEVICE_TREE) += device_tree.c + romstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index 4f5cc07..5087d39 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -12,9 +12,12 @@ #include <string.h> #include <stddef.h> #include <stdlib.h> +#include <limits.h> #define FDT_PATH_MAX_DEPTH 10 // should be a good enough upper bound #define FDT_PATH_MAX_LEN 128 // should be a good enough upper bound +#define FDT_MAX_MEMORY_NODES 4 // should be a good enough upper bound +#define FDT_MAX_MEMORY_REGIONS 16 // should be a good enough upper bound /* * Functions for picking apart flattened trees. @@ -504,6 +507,96 @@ } /* + * fdt_read_memory_regions finds memory ranges from a flat device-tree + * + * @params blob address of FDT + * @params regions all regions that are read inside the reg property of + * memory nodes are saved inside this array + * @params regions_count maximum number of entries that can be saved inside + * the regions array. + * + * Returns: Either 0 on error or returns the number of regions put into the regions array. + */ +size_t fdt_read_memory_regions(const void *blob, + struct device_tree_region regions[], + size_t regions_count) +{ + u32 node, root, addrcp, sizecp; + u32 nodes[FDT_MAX_MEMORY_NODES] = {0}; + size_t region_idx = 0; + size_t node_count = 0; + + if (!fdt_is_valid(blob)) + return 0; + + node = fdt_find_node_by_path(blob, "/memory", &addrcp, &sizecp); + if (node) { + region_idx += fdt_read_reg_prop(blob, node, addrcp, sizecp, + regions, regions_count); + if (region_idx >= regions_count) { + printk(BIOS_WARNING, "FDT: Too many memory regions\n"); + goto out; + } + } + + root = fdt_find_node_by_path(blob, "/", &addrcp, &sizecp); + node_count = fdt_find_subnodes_by_prefix(blob, root, "memory@", + &addrcp, &sizecp, nodes, + FDT_MAX_MEMORY_NODES); + if (node_count >= FDT_MAX_MEMORY_NODES) { + printk(BIOS_WARNING, "FDT: Too many memory nodes\n"); + /* Can still reading the regions for those we got */ + } + + for (size_t i = 0; i < MIN(node_count, FDT_MAX_MEMORY_NODES); i++) { + region_idx += fdt_read_reg_prop(blob, nodes[i], addrcp, sizecp, + &regions[region_idx], + regions_count - region_idx); + if (region_idx >= regions_count) { + printk(BIOS_WARNING, "FDT: Too many memory regions\n"); + goto out; + } + } + +out: + for (size_t i = 0; i < MIN(region_idx, regions_count); i++) { + printk(BIOS_DEBUG, "FDT: Memory region [%#llx - %#llx]\n", + regions[i].addr, regions[i].addr + regions[i].size); + } + + return region_idx; +} + +/* + * fdt_get_memory_top finds top of memory from a flat device-tree + * + * @params blob address of FDT + * + * Returns: Either 0 on error or returns the maximum memory address + */ +uint64_t fdt_get_memory_top(const void *blob) +{ + struct device_tree_region regions[FDT_MAX_MEMORY_REGIONS] = {0}; + uint64_t top = 0; + uint64_t total = 0; + size_t count; + + if (!fdt_is_valid(blob)) + return 0; + + count = fdt_read_memory_regions(blob, regions, FDT_MAX_MEMORY_REGIONS); + for (size_t i = 0; i < MIN(count, FDT_MAX_MEMORY_REGIONS); i++) { + top = MAX(top, regions[i].addr + regions[i].size); + total += regions[i].size; + } + + printk(BIOS_DEBUG, "FDT: Found %u MiB of RAM\n", + (uint32_t)(total / MiB)); + + return top; +} + +/* * Functions to turn a flattened tree into an unflattened one. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 8 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/1796536c_5c998d6b?us… : PS10, Line 205: & > > What if the address is below 4G (the high dword is zero, but the low dword is non-zero)? Is this a valid value? > > do you mean above 4G? where MSB is non-zero and LSB is zero ? I mean MSB is zero and LSB is non-zero, but the scenario you suggested is also a problem with this check. This is how I would implement the check: ```suggestion if (!dw1 && !dw0) { ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 15:15:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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