coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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3527 discussions

[L] Change in coreboot[main]: mb/dell: Add OptiPlex 7020/9020 port
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Felix Singer, Leah Rowe, Máté Kukri, Nicholas Chin. Nico Huber has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 35: (1 comment) Patchset: PS35: > I have compiled and flashed this patch (patchset 31) through Libreboot on for my Dell 9020 SFF conta […] Try this: CB:82787. -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 35 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ben Westover <me(a)benthetechguy.net> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Name of user not set #1005484 Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-CC: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Name of user not set #1005484

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb.c: Align native current map with MRC
by Keith Hui (Code Review) 03 Jun '24

03 Jun '24

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82754?usp=email ) Change subject: sb/intel/bd82x6x/early_usb.c: Align native current map with MRC ...................................................................... Patch Set 1: (1 comment) File util/autoport/bd82x6x.go: https://review.coreboot.org/c/coreboot/+/82754/comment/d04e439f_29ec2401?us… : PS1, Line 315: 0x20000553 > 8 is missing This is intentional. #8 maps to _DEFAULT (#1) after all macros are resolved, so autoport will output 1 anyway. I allocated #8 to it as well so MRC can be fed 0x40 or 0x80 as needed based on PCH type and USBIR still gets _DEFAULT. If I put 8 here there will be duplicate. If one needs to use MRC for their boards, I expect them to read the comments in early_usb_mrc.c and put 8 there manually. -- To view, visit https://review.coreboot.org/c/coreboot/+/82754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Gerrit-Change-Number: 82754 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:13:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: nb/intel/haswell: Synchronize lists of graphics PCI IDs
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82787?usp=email ) Change subject: nb/intel/haswell: Synchronize lists of graphics PCI IDs ...................................................................... nb/intel/haswell: Synchronize lists of graphics PCI IDs Both, the list of IDs that we hooked our driver up to and the list that we use for VBIOS mapping, had gaps. Fill those. Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/haswell/gma.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/82787/1 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 9e9f980..f7fad31 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -93,12 +93,14 @@ case 0x80860406: /* GT1 Mobile */ case 0x8086040a: /* GT1 Server */ case 0x80860a06: /* GT1 ULT */ + case 0x80860a0e: /* GT1 ULX */ case 0x80860412: /* GT2 Desktop */ case 0x80860416: /* GT2 Mobile */ case 0x8086041a: /* GT2 Server */ case 0x8086041e: /* GT1.5 Desktop */ case 0x80860a16: /* GT2 ULT */ + case 0x80860a1e: /* GT2 ULX */ case 0x80860422: /* GT3 Desktop */ case 0x80860426: /* GT3 Mobile */ @@ -485,6 +487,9 @@ 0x0406, /* Mobile GT1 */ 0x0416, /* Mobile GT2 */ 0x0426, /* Mobile GT3 */ + 0x040a, /* Server GT1 */ + 0x041a, /* Server GT2 */ + 0x042a, /* Server GT3 */ 0x0d16, /* Mobile 4+3 GT1 */ 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ 0x0d36, /* Mobile 4+3 GT3 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad Gerrit-Change-Number: 82787 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config
by Patrick Rudolph (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Keith Hui. Patrick Rudolph has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82655?usp=email ) Change subject: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/c/coreboot/+/82655/comment/c8e5a0ac_2228445d?us… : PS3, Line 19: 0x50 > It hints at the reason why I call for this - anything over the array's size go directly to USBIR, an […] Ok, got it. BTW is there any board making use of the "direct" USBIRx value in devicetree? -- To view, visit https://review.coreboot.org/c/coreboot/+/82655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Gerrit-Change-Number: 82655 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:07:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config
by Keith Hui (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Patrick Rudolph. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82655?usp=email ) Change subject: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/c/coreboot/+/82655/comment/cd18eb46_ef313371?us… : PS3, Line 19: 0x50 > I don't understand this comment It hints at the reason why I call for this - anything over the array's size go directly to USBIR, and the lowest value so far is 0x53. I guess I am being too specific. -- To view, visit https://review.coreboot.org/c/coreboot/+/82655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Gerrit-Change-Number: 82655 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:00:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (3 comments) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/ac0df1e4_414ad3de?us… : PS10, Line 205: & > I am reading the value in the CRASHLOG_HEADER and CRASHLOG_CAPABILITY_STATUS registers and populatin […] Ah, it's two separate registers... Later stored as a single 64-bit value for reasons I cannot comprehend. Oh, well. In that case, can we *not* name these variables `dw0` and `dw1`, please? `cl_header` and `cl_cap_status` would make the code substantially easier to follow. https://review.coreboot.org/c/coreboot/+/82136/comment/1aa5aef0_b317da92?us… : PS10, Line 215: : for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { : cur_offset = 16 + 8*i; : cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + : cur_offset)) + ((u64)read32((u32 *) : (disc_tab_addr + cur_offset + 4)) << 32)); This code makes little sense. Why is it using arrays of 64-bit values to store stuff that gets read as 32-bit values? ```suggestion for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { const uintptr_t cur_addr = (uintptr_t)disc_tab_addr + 16 + 8 * i; cpu_cl_disc_tab.buffers[i].data = (u64)read32p(cur_addr) | (u64)read32p(cur_addr + 4) << 32); ``` https://review.coreboot.org/c/coreboot/+/82136/comment/4635d739_eaed2bd2?us… : PS10, Line 248: if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, cpu_bar_addr); : } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, cpu_bar_addr); : } else { : printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", : cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); : return false; : } > The intention here is to write the temp address (cpu_bar_addr) in both PCI_BASE_ADDRESS_0 and PCI_BA […] If you assign the same base address to both BARs, don't you end up with a resource conflict? -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 17:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: sio/nuvoton: Implement a common ramstage ACPI LDN helper
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Keith Hui, Paul Menzel. Nico Huber has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82632?usp=email ) Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper ...................................................................... Patch Set 6: Code-Review+1 (2 comments) Patchset: PS5: > Maybe rip the aux device part out of pc_keyboard_init(), and when the conditions are right, swap the […] Sounds like a plan, but I guess I'm out of my depth here. Can't remember having ever programmed anything related to the aux part. If you write a patch, maybe add Patrick Rudolph, IIRC he did some related work on libpayload. File src/superio/nuvoton/common/common.c: https://review.coreboot.org/c/coreboot/+/82632/comment/db3581be_28226190?us… : PS6, Line 79: * Clear case open pin 0 status. Looks like I forgot to ask before. Why would we do this? Doesn't it mean the user can't be informed (e.g. when running an appropriate OS tool)?. -- To view, visit https://review.coreboot.org/c/coreboot/+/82632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd Gerrit-Change-Number: 82632 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 17:48:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/dell: Add OptiPlex 7020/9020 port
by Name of user not set (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Leah Rowe, Máté Kukri. Name of user not set #1005484 has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 35: (1 comment) Patchset: PS35: I have compiled and flashed this patch (patchset 31) through Libreboot on for my Dell 9020 SFF containing a Xeon E3-1246 v3 processor. Both the GRUB and SeaBIOS versions of both the Framebuffer and text variants DO boot into the OS (Pure OS for me), but during the boot, nothing is shown on screen and the monitor is NOT synced. I guess this is not Libreboot specific but Xeon v3, as it has also been noted by someone who compiled Coreboot + EDK2 directly form source: https://www.reddit.com/r/coreboot/comments/137tbxy/comment/jjl1e14/ -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 35 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ben Westover <me(a)benthetechguy.net> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Name of user not set #1005484 Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-CC: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 17:36:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/xcompile: Use new GCC's commande options only if supported
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Elyes Haouas, Martin L Roth, Paul Menzel. Nico Huber has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82785?usp=email ) Change subject: util/xcompile: Use new GCC's commande options only if supported ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Patchset: PS1: Note, CB:82786 needs to land first. Commit Message: https://review.coreboot.org/c/coreboot/+/82785/comment/9883c05e_e1c6cc9c?us… : PS1, Line 7: commande *command* or maybe `*warning options*' -- To view, visit https://review.coreboot.org/c/coreboot/+/82785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6 Gerrit-Change-Number: 82785 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Jun 2024 17:29:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Elyes Haouas. Nico Huber has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82786?usp=email ) Change subject: tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n) ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Gerrit-Change-Number: 82786 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Jun 2024 17:28:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit June 2024