coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Sowmya Aralguppe (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Angel Pons, Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (3 comments) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/a6e67526_6c7c14c4?us… : PS10, Line 205: & > Ah, it's two separate registers... […] ACK . I will change to meaningful names as suggested. This check was introduced so that it fails early rather than later and both the registers should have non zero values for crashlog to function properly. yes cl_header and cl_cap_status is packed into 64 bits - cpu_crashlog_header_t in crashlog.h https://review.coreboot.org/c/coreboot/+/82136/comment/f7bb0af5_fa563b16?us… : PS10, Line 215: : for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { : cur_offset = 16 + 8*i; : cpu_cl_disc_tab.buffers[i].data = ((u64)read32((u32 *)(disc_tab_addr + : cur_offset)) + ((u64)read32((u32 *) : (disc_tab_addr + cur_offset + 4)) << 32)); > This code makes little sense. […] Here the loop is for number of child crash logs that are connected to the record. For each child there is a base offset and buffer size .These are 48 bits and hence gets assigned to 64bit values. Bits Access Default Description 31:0 RW 0 DATA_BUFFER_ADDRESS Base address within this BAR for the crashlog data buffer. 47:32 RW 0x700 DATA_BUFFER_SIZE https://review.coreboot.org/c/coreboot/+/82136/comment/d6fb65b0_25ede08f?us… : PS10, Line 248: if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, cpu_bar_addr); : } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, cpu_bar_addr); : } else { : printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", : cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); : return false; : } > If you assign the same base address to both BARs, don't you end up with a resource conflict? Designated Vendor-Specific Extended Capability (DVSEC) specifications for crashlog specifies 98:96 bits as tbir .When tbir is 0 the bar address PM_BAR is read from 0x10 (PCI_BASE_ADDRESS_0) and if its 1 ,it should be read from 0x14 (PCI_BASE_ADDRESS_1).For RPL the PM_BAR is 0x10 by default but to keep it aligned to common code it is good to read tbir and then read from either PCI_BASE_ADDRESS_0 or PCI_BASE_ADDRESS_1.So we write the temporary hard coded bar address to both these offsets. so to summarize either one of the BAR address is read based on capability reg so there wont be any resource conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 19:04:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82786?usp=email ) Change subject: tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n) ...................................................................... tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n) Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/irq/irq.c M src/southbridge/intel/common/rcba_pirq.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index 4ffe138..386538e 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -373,7 +373,7 @@ if (!cached_entries) return false; - pin_irq_map = calloc(MAX_SLOTS, sizeof(struct slot_pin_irq_map) * PCI_INT_MAX); + pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map)); pirq_map.type = PIRQ_GSI; legacy_pirq_routing = lpc_get_pic_pirq_routing(&pirq_routes); diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index c9ab140..956fe63 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -59,7 +59,7 @@ printk(BIOS_DEBUG, "Generating ACPI PIRQ entries\n"); - pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); + pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map)); pirq_map.type = PIRQ_SOURCE_PATH; for (i = 0; i < PIRQ_COUNT; i++) snprintf(pirq_map.source_path[i], sizeof(pirq_map.source_path[i]), -- To view, visit https://review.coreboot.org/c/coreboot/+/82786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Gerrit-Change-Number: 82786 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/xcompile: Use new GCC's warning options only if supported
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Martin L Roth, Paul Menzel. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82785?usp=email ) Change subject: util/xcompile: Use new GCC's warning options only if supported ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82785/comment/6ec54eb0_2f0fd552?us… : PS1, Line 7: commande > *command* […] "commande" is command in french :)))) Done, Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/82785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6 Gerrit-Change-Number: 82785 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 19:02:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: util/xcompile: Use new GCC's warning options only if supported
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Elyes Haouas, Martin L Roth, Paul Menzel. Hello Martin L Roth, Nico Huber, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82785?usp=email to look at the new patch set (#3). Change subject: util/xcompile: Use new GCC's warning options only if supported ...................................................................... util/xcompile: Use new GCC's warning options only if supported Wflex-array-member-not-at-end & Wcalloc-transposed-args are not supported when using GCC older than GCC-14. Use them only when supported. Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/xcompile/xcompile 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/82785/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I11c1e729569c8130bd254a10454c5066a72974d6 Gerrit-Change-Number: 82785 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: nb/intel/haswell: Synchronize lists of graphics PCI IDs
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Nico Huber. Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/82787?usp=email ) Change subject: nb/intel/haswell: Synchronize lists of graphics PCI IDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I97c09bb113cf0f35ae158abbd0ba2632dbad7cad Gerrit-Change-Number: 82787 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:54:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: sio/nuvoton: Implement a common ramstage ACPI LDN helper
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Keith Hui, Paul Menzel. Nico Huber has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82632?usp=email ) Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper ...................................................................... Patch Set 6: (1 comment) File src/superio/nuvoton/common/common.c: https://review.coreboot.org/c/coreboot/+/82632/comment/fa8df7a6_644e5f34?us… : PS6, Line 79: * Clear case open pin 0 status. > Just put it in a known state. […] But how if we clear it on boot? Assuming somebody opened the case, tampered, closed again, user boots, we clear it, how'd the user know? -- To view, visit https://review.coreboot.org/c/coreboot/+/82632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd Gerrit-Change-Number: 82632 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[L] Change in coreboot[main]: mb/dell: Add OptiPlex 7020/9020 port
by Máté Kukri (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Felix Singer, Leah Rowe, Nicholas Chin. Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/55232?usp=email ) Change subject: mb/dell: Add OptiPlex 7020/9020 port ...................................................................... Patch Set 35: (1 comment) Patchset: PS35: > Try this: CB:82787. @Gusher123 please try the patch Nico pointed out, I also had the missing gfx id issue a long time ago with a less common i3, and this sounds identical to that. -- To view, visit https://review.coreboot.org/c/coreboot/+/55232?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 35 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ben Westover <me(a)benthetechguy.net> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Name of user not set #1005484 Gerrit-CC: ilikenwf <mparnell(a)gmail.com> Gerrit-CC: nat ✨ <nat(a)nekopon.pl> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Name of user not set #1005484

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[XS] Change in coreboot[main]: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP
by Nico Huber (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar. Nico Huber has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82781?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/82781/comment/447e2885_b4816ac8?us… : PS4, Line 119: select HAVE_INTEL_FSP_REPO if FSP_TYPE_IOT Currently none of the ADL-N boards select FSP_TYPE_IOT. Do we know if this is correct or rather an oversight because it wasn't necessary before? -- To view, visit https://review.coreboot.org/c/coreboot/+/82781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Gerrit-Change-Number: 82781 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:27:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config
by Keith Hui (Code Review) 03 Jun '24

03 Jun '24

Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82655?usp=email ) Change subject: sb/intel/bd82x6x: Allow actual USBIRx values for native USB config ...................................................................... Patch Set 3: (1 comment) File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/c/coreboot/+/82655/comment/b5b51c24_7c25e897?us… : PS3, Line 19: 0x50 > Ok, got it. […] Not yet, but since I also patched autoport (see this train) to just put any unrecognized values direct, we will get there. -- To view, visit https://review.coreboot.org/c/coreboot/+/82655?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Gerrit-Change-Number: 82655 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:23:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[M] Change in coreboot[main]: sio/nuvoton: Implement a common ramstage ACPI LDN helper
by Keith Hui (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Nico Huber, Paul Menzel. Keith Hui has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82632?usp=email ) Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper ...................................................................... Patch Set 6: (2 comments) Patchset: PS5: > Sounds like a plan, but I guess I'm out of my depth here. Can't remember having […] Acknowledged File src/superio/nuvoton/common/common.c: https://review.coreboot.org/c/coreboot/+/82632/comment/872c6651_97e1abca?us… : PS6, Line 79: * Clear case open pin 0 status. > Looks like I forgot to ask before. Why would we do this? Doesn't it mean the […] Just put it in a known state. Feature is not inhibited and users can still be informed via the hwmon interface eg. lm_sensors. -- To view, visit https://review.coreboot.org/c/coreboot/+/82632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd Gerrit-Change-Number: 82632 Gerrit-PatchSet: 6 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 18:17:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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coreboot-gerrit June 2024