coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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3527 discussions

[S] Change in coreboot[main]: mb/google/brya: Create a tereid variant
by Subrata Banik (Code Review) 21 Jun '24

21 Jun '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Nick Vaccaro, V Sowmya. Subrata Banik has posted comments on this change by V Sowmya. ( https://review.coreboot.org/c/coreboot/+/83145?usp=email ) Change subject: mb/google/brya: Create a tereid variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I052c3ba93d00e2df7e205c3127210bacaa956ca0 Gerrit-Change-Number: 83145 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 07:06:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures
by Sowmya Aralguppe (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Angel Pons, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Pratikkumar V Prajapati, Subrata Banik, Tarun. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83106?usp=email ) Change subject: soc/intel: Enable crashlog IP for both 32-bit and 64-bit architectures ...................................................................... Patch Set 19: (1 comment) File src/soc/intel/common/block/crashlog/crashlog.c: https://review.coreboot.org/c/coreboot/+/83106/comment/3caea52b_7ddd1d3f?us… : PS15, Line 321: sizeof(uintptr_t) > > > I have changed dest_addr to be u32 *,IMHO that is right solution […] no sorry - in my local copy src_address is incremented by 4 since we are reading dw and it is uintptr_t (we can keep it as u32 * also -doesnt matter) - while upstreaming probably i made a mistake -- To view, visit https://review.coreboot.org/c/coreboot/+/83106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I552257d3770abb409e2dcd8a13392506b5e7feb7 Gerrit-Change-Number: 83106 Gerrit-PatchSet: 19 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 06:53:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/lotso: GPP_B14 used for buzzer
by Jian Tong (Code Review) 20 Jun '24

20 Jun '24

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83147?usp=email ) Change subject: mb/google/brox/var/lotso: GPP_B14 used for buzzer ...................................................................... mb/google/brox/var/lotso: GPP_B14 used for buzzer ALC257 does not supoort built-in digtal buzzer, So use external pwm to PCBEEP for beep sound. BUG=b:346956771 BRANCH=None TEST=emerge-brox coreboot sys-boot/chromeos-bootimage firmware-shell: devbeep -> can output beep normally. Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Signed-off-by: Jing Tong <tongjian(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brox/variants/lotso/gpio.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/83147/1 diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c index 230ecaf..c85363d 100644 --- a/src/mainboard/google/brox/variants/lotso/gpio.c +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -7,6 +7,9 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 + * NF6: USB_C_GPP_B14] ==> ACZ_SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_REFCLK_SSD1_REQ_N */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SOC_GPP_E10 (NC) */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5 Gerrit-Change-Number: 83147 Gerrit-PatchSet: 1 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/brya/var/nivviks: Enable PCIe Wifi Gpios based on fw_config
by Paul Menzel (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Poornima Tom, Poornima Tom, V Sowmya. Paul Menzel has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83077?usp=email ) Change subject: mb/google/brya/var/nivviks: Enable PCIe Wifi Gpios based on fw_config ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83077/comment/30578163_a563d9d6?us… : PS10, Line 7: Gpios GPIOs -- To view, visit https://review.coreboot.org/c/coreboot/+/83077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0584e91b5143c6df742961657d242c046409b3a Gerrit-Change-Number: 83077 Gerrit-PatchSet: 10 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 05:10:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/nivviks: Add wake config for CNVi
by Paul Menzel (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Poornima Tom, Poornima Tom, V Sowmya. Paul Menzel has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83138?usp=email ) Change subject: mb/google/brya/var/nivviks: Add wake config for CNVi ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/83138/comment/3fd2e5ca_3d762c07?us… : PS3, Line 9: Added Add https://review.coreboot.org/c/coreboot/+/83138/comment/5229c3f2_9d06bf92?us… : PS3, Line 9: Also, set 'add_acpi_dma_property' to : true. : Why? -- To view, visit https://review.coreboot.org/c/coreboot/+/83138?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d Gerrit-Change-Number: 83138 Gerrit-PatchSet: 3 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 21 Jun 2024 05:09:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Add FSP-I and FSP-O
by Paul Menzel (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Andrey Petrov, Patrick Rudolph, Ronak Kanabar, Subrata Banik. Paul Menzel has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/83113?usp=email ) Change subject: drivers/intel/fsp2_0: Add FSP-I and FSP-O ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83113/comment/216235f1_2fcbc943?us… : PS1, Line 11: Add the summary from your comment? > An FSP may include optional OEM components that provide OEM extensibility. This component shall have an FSP_INFO_HEADER with component type in Image attribute field set to FSP-O -- To view, visit https://review.coreboot.org/c/coreboot/+/83113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53ed1eb45eac89d72ae472fe2b41d64c5eecb182 Gerrit-Change-Number: 83113 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 05:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: acpigen_ps2_keybd: Support an Accessibility key
by Paul Menzel (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Aseda Aboagye, Cliff Huang, Forest Mittelberg, Lance Zhao, Tim Wawrzynczak. Paul Menzel has posted comments on this change by Aseda Aboagye. ( https://review.coreboot.org/c/coreboot/+/82996?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: acpigen_ps2_keybd: Support an Accessibility key ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82996/comment/bb45093b_6651439b?us… : PS2, Line 15: Linux kernel with patches Please reference them. -- To view, visit https://review.coreboot.org/c/coreboot/+/82996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc639b37e89ec251f55859331ab5c2f4b2b45a7d Gerrit-Change-Number: 82996 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 04:27:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7
by Subrata Banik (Code Review) 20 Jun '24

20 Jun '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Poornima Tom, Poornima Tom, Pranava Y N, V Sowmya. Subrata Banik has posted comments on this change by Poornima Tom. ( https://review.coreboot.org/c/coreboot/+/83074?usp=email ) Change subject: mb/google/brya/var/nivviks: Add fw_config fields for wifi6 and wifi7 ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83074/comment/64242f66_2dd73018?us… : PS6, Line 7: brya > but we decide put the really mb name instead the path, since many projects under brya +1 to Eric, just specify the baseboard here and not the actual directory structure. -- To view, visit https://review.coreboot.org/c/coreboot/+/83074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76 Gerrit-Change-Number: 83074 Gerrit-PatchSet: 6 Gerrit-Owner: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Poornima Tom <poornima.tom(a)intel.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 21 Jun 2024 03:31:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[S] Change in coreboot[main]: soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiB
by Subrata Banik (Code Review) 20 Jun '24

20 Jun '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83112?usp=email ) Change subject: soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiB ...................................................................... soc/intel/cmn/acpi: Add support for `PCR_BASE_ADDRESS` above 4 GiB This change updates the Northbridge ASL to conditionally include a QWordMemory resource for `SM01` when the `CONFIG_PCR_BASE_ADDRESS` is above 4 GiB. If `CONFIG_PCR_BASE_ADDRESS` is below 4 GiB, or falls within the PCH reserved range, the existing handling of `SM01` remains unchanged (as a DWordMemory resource). TEST=Built with CONFIG_PCR_BASE_ADDRESS both above and below 4 GiB, verified ASL output. Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83112 Reviewed-by: Cliff Huang <cliff.huang(a)intel.com> Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 14 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Hannah Williams: Looks good to me, but someone else must approve Cliff Huang: Looks good to me, but someone else must approve Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 03295b4..51b0e23 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -166,7 +166,12 @@ 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02) -#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ +#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB)) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x000000000, 0x00000000, 0x00000000, + 0x00000000,,, SM01) +#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) /* SBREG BAR if outside of PCH reserved resource */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, @@ -202,13 +207,19 @@ PMIN = \_SB.PCI0.MCHC.TLUD & (0xfff << 20) PLEN = PMAX - PMIN + 1 -#if !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ +#if (CONFIG_PCR_BASE_ADDRESS >= (4ULL * GiB)) + CreateQwordField (MCRS, SM01._MIN, SMIN) + CreateQwordField (MCRS, SM01._MAX, SMAX) + CreateQwordField (MCRS, SM01._LEN, SLEN) + SMIN = P2SB_BAR + SLEN = P2SB_SIZE + SMAX = SMIN + SLEN - 1 +#elif !((CONFIG_PCR_BASE_ADDRESS >= PCH_PRESERVED_BASE_ADDRESS) && \ (CONFIG_PCR_BASE_ADDRESS < PCH_PRESERVED_BASE_ADDRESS + PCH_PRESERVED_BASE_SIZE)) /* Fix up SBREG BAR memory region if outside PCH reserved resource */ CreateDwordField (MCRS, SM01._MIN, SMIN) CreateDwordField (MCRS, SM01._MAX, SMAX) CreateDwordField (MCRS, SM01._LEN, SLEN) - SMIN = P2SB_BAR SLEN = P2SB_SIZE SMAX = SMIN + SLEN - 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/83112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9547377cdea6cb4334ab59b3bc837059fbb22e3b Gerrit-Change-Number: 83112 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: util/ifdtool: Add Panther Lake platform support under IFDv2
by Subrata Banik (Code Review) 20 Jun '24

20 Jun '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83141?usp=email ) Change subject: util/ifdtool: Add Panther Lake platform support under IFDv2 ...................................................................... util/ifdtool: Add Panther Lake platform support under IFDv2 BUG=b:347669091 TEST=Able to build ifdtool. Change-Id: Id261898932f11f4c9066453bce18fd889996e171 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83141 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M util/ifdtool/ifdtool.c M util/ifdtool/ifdtool.h 2 files changed, 27 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index c04d504..1c3e810 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -271,6 +271,8 @@ return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT; case PLATFORM_MTL: return CHIPSET_800_SERIES_METEOR_LAKE; + case PLATFORM_PTL: + return CHIPSET_900_SERIES_PANTHER_LAKE; case PLATFORM_ICL: return CHIPSET_400_SERIES_ICE_POINT; case PLATFORM_LBG: @@ -306,6 +308,7 @@ PLATFORM_SKLKBL, PLATFORM_IFD2, PLATFORM_MTL, + PLATFORM_PTL, PLATFORM_WBG, }; unsigned int i; @@ -562,6 +565,7 @@ switch (chipset) { case CHIPSET_500_600_SERIES_TIGER_ALDER_POINT: case CHIPSET_800_SERIES_METEOR_LAKE: + case CHIPSET_900_SERIES_PANTHER_LAKE: _decode_spi_frequency_500_series(freq); break; default: @@ -640,12 +644,17 @@ static void decode_espi_frequency(unsigned int freq) { - if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT) + switch (chipset) { + case CHIPSET_500_600_SERIES_TIGER_ALDER_POINT: _decode_espi_frequency_500_series(freq); - else if (chipset == CHIPSET_800_SERIES_METEOR_LAKE) + break; + case CHIPSET_800_SERIES_METEOR_LAKE: + case CHIPSET_900_SERIES_PANTHER_LAKE: _decode_espi_frequency_800_series(freq); - else + break; + default: _decode_espi_frequency(freq); + } } static void decode_component_density(unsigned int density) @@ -695,7 +704,7 @@ static int is_platform_with_100x_series_pch(void) { if (chipset >= CHIPSET_100_200_SERIES_SUNRISE_POINT && - chipset <= CHIPSET_800_SERIES_METEOR_LAKE) + chipset <= CHIPSET_900_SERIES_PANTHER_LAKE) return 1; return 0; @@ -724,6 +733,8 @@ freq = (fpsba->pchstrp[22] & 0x38) >> 3; else if (chipset == CHIPSET_800_SERIES_METEOR_LAKE) freq = (fpsba->pchstrp[65] & 0x38) >> 3; + else if (chipset == CHIPSET_900_SERIES_PANTHER_LAKE) + freq = (fpsba->pchstrp[119] & 0x38) >> 3; else freq = (fcba->flcomp >> 17) & 7; decode_espi_frequency(freq); @@ -1021,7 +1032,8 @@ } if (chipset == CHIPSET_500_600_SERIES_TIGER_ALDER_POINT || - chipset == CHIPSET_800_SERIES_METEOR_LAKE) { + chipset == CHIPSET_800_SERIES_METEOR_LAKE || + chipset == CHIPSET_900_SERIES_PANTHER_LAKE) { printf("FLMAP3: 0x%08x\n", fdb->flmap3); printf(" Minor Revision ID: 0x%04x\n", (fdb->flmap3 >> 14) & 0x7f); printf(" Major Revision ID: 0x%04x\n", (fdb->flmap3 >> 21) & 0x7ff); @@ -1379,6 +1391,7 @@ case PLATFORM_TGL: case PLATFORM_ADL: case PLATFORM_MTL: + case PLATFORM_PTL: return true; default: return false; @@ -1443,6 +1456,7 @@ case PLATFORM_ADL: case PLATFORM_IFD2: case PLATFORM_MTL: + case PLATFORM_PTL: /* CPU/BIOS can read descriptor and BIOS. */ fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; @@ -1596,6 +1610,7 @@ case PLATFORM_TGL: case PLATFORM_ADL: case PLATFORM_MTL: + case PLATFORM_PTL: data_offset = 0x18; break; default: @@ -1624,6 +1639,9 @@ case PLATFORM_MTL: gpr0_offset = 0x40; break; + case PLATFORM_PTL: + gpr0_offset = 0x76; + break; default: break; } @@ -2470,6 +2488,8 @@ platform = PLATFORM_IFD2; } else if (!strcmp(optarg, "mtl")) { platform = PLATFORM_MTL; + } else if (!strcmp(optarg, "ptl")) { + platform = PLATFORM_PTL; } else if (!strcmp(optarg, "wbg")) { platform = PLATFORM_WBG; } else { diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 79fe0ab..ef37ca7 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -39,6 +39,7 @@ CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP) * variants onwards */ CHIPSET_800_SERIES_METEOR_LAKE, /* 14th gen Core i/o (LP) variants onwards */ + CHIPSET_900_SERIES_PANTHER_LAKE, /* 16th gen Core i/o (LP) variants onwards */ CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_DENVERTON, }; @@ -57,6 +58,7 @@ PLATFORM_IFD2, PLATFORM_DNV, PLATFORM_MTL, + PLATFORM_PTL, PLATFORM_WBG }; -- To view, visit https://review.coreboot.org/c/coreboot/+/83141?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id261898932f11f4c9066453bce18fd889996e171 Gerrit-Change-Number: 83141 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit June 2024