Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/82601?usp=email )
Change subject: util/autoport: Clean up header files in generated files
......................................................................
Patch Set 1:
(1 comment)
File util/autoport/bd82x6x.go:
https://review.coreboot.org/c/coreboot/+/82601/comment/febf4a41_c0601277?us… :
PS1, Line 300: #include <northbridge/intel/sandybridge/raminit_native.h>
CB:82405 also removes this
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Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82601?usp=email )
Change subject: util/autoport: Clean up header files in generated files
......................................................................
util/autoport: Clean up header files in generated files
Remove header files that no longer exist, or are unnecessary.
- early_init.c: Remove raminit_native.h, which was deleted in commit
0f8cd41be1fe (nb/intel/sandybridge: Drop raminit_native.h)
- mainboard.c: Remove southbridge/intel/bd82x6x/pch.h as it is unused.
This was previously used to configure a few registers in SPIBAR, but
these have since been moved to PCH code and the devicetree.
Change-Id: I904c95394b4fea73b4990342e647595b5f10335f
Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com>
---
M util/autoport/bd82x6x.go
1 file changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/82601/1
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index 76411e7..271e592 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -194,9 +194,6 @@
Value: "\\_SB.PCI0.GFX0.DECB",
})
- /* SPI init */
- MainboardIncludes = append(MainboardIncludes, "southbridge/intel/bd82x6x/pch.h")
-
FADT := ctx.InfoSource.GetACPI()["FACP"]
pcieHotplugMap := "{ "
@@ -297,7 +294,6 @@
sb.WriteString(`
#include <bootblock_common.h>
#include <device/pci_ops.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
`)
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Brandon Weeks has posted comments on this change by Brandon Weeks. ( https://review.coreboot.org/c/coreboot/+/81595?usp=email )
Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
......................................................................
Patch Set 12:
(2 comments)
File src/mainboard/cwwk/adl/Kconfig:
https://review.coreboot.org/c/coreboot/+/81595/comment/08e8f120_34d85146?us… :
PS10, Line 9: select HAVE_ACPI_RESUME
> If S3 isn't working, it might be a good idea to temporarily comment this out: […]
https://gist.github.com/brandonweeks/36e440f065eb520993dd267b5438b3c2
S3 does appear to work upon testing, S0ix however does not.
File src/mainboard/cwwk/adl/romstage_fsp_params.c:
https://review.coreboot.org/c/coreboot/+/81595/comment/c8e177ad_c68986d5?us… :
PS10, Line 23: [1] = { .addr_dimm[0] = 0x52, },
> If the board only has one DIMM slot, then only one of these lines is needed. […]
Done
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Attention is currently required from: Angel Pons, Brandon Weeks, Federico Amedeo Izzo, Felix Singer, Joel Linn, Paul Menzel.
Hello Angel Pons, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins)
Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
......................................................................
mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE
ports, similar boards are available in other port configurations. As a
low cost, relatively high performance board with 4 NICs, it is well
suited for networking or 'homelab' tasks.
CPU: Intel N100 or N350
Memory: DDR5-4800 SODIMM (max 16 GB)
NIC: 4x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 4x Ethernet
- Display Port
- HDMI
- 4x USB 2.0
- Micro SD
Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- DisplayPort / HDMI
- 4x Intel I226 2.5 GbE NICs
- M.2 ports
- Micro SD slot
- ACPI S3
Not working / not tested:
- Fan (ITE IT8613E)
- Audio
- S0ix
- Internal USB ports
VBT extracted from vendor UEFI firmware version ADLN 0.01 x64
(04/04/2023 11:42:38).
Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be
Signed-off-by: Brandon Weeks <me(a)brandonweeks.com>
---
A src/mainboard/cwwk/Kconfig
A src/mainboard/cwwk/Kconfig.name
A src/mainboard/cwwk/adl/Kconfig
A src/mainboard/cwwk/adl/Kconfig.name
A src/mainboard/cwwk/adl/Makefile.mk
A src/mainboard/cwwk/adl/board_info.txt
A src/mainboard/cwwk/adl/bootblock.c
A src/mainboard/cwwk/adl/data.vbt
A src/mainboard/cwwk/adl/devicetree.cb
A src/mainboard/cwwk/adl/dsdt.asl
A src/mainboard/cwwk/adl/gpio.h
A src/mainboard/cwwk/adl/mainboard.c
A src/mainboard/cwwk/adl/romstage_fsp_params.c
13 files changed, 520 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/12
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Hello Angel Pons, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
......................................................................
mb/cwwk: Add CWWK CW-ADL-4L-V1.0 board
This board is the CWWK variant based upon Alder Lake with 4 2.5 GbE
ports, similar boards are available in other port configurations. As a
low cost, relatively high performance board with 4 NICs, it is well
suited for networking or 'homelab' tasks.
CPU: Intel N100 or N350
Memory: DDR5-4800 SODIMM (max 16 GB)
NIC: 4x Intel I226-V 2.5 GbE
Expansion:
- M.2 2230 E key
- M.2 2280 M key
- USB 2.0 header
- Fan header
External ports:
- DC power
- 4x Ethernet
- Display Port
- HDMI
- 4x USB 2.0
- Micro SD
Working:
- Boots Debian 12 with SeaBIOS and EDK II payloads
- Serial port
- External USB ports
- DisplayPort / HDMI
- 4x Intel I226 2.5 GbE NICs
- M.2 ports
- Micro SD slot
- ACPI S3
Not working / not tested:
- Fan (ITE IT8613E)
- Audio
- S0ix
- Internal USB ports
VBT extracted from vendor UEFI firmware version ADLN 0.01 x64
(04/04/2023 11:42:38).
Change-Id: Ice9174d95c10afc6a22ddd15fb3be4fa38d329be
Signed-off-by: Brandon Weeks <me(a)brandonweeks.com>
---
A src/mainboard/cwwk/Kconfig
A src/mainboard/cwwk/Kconfig.name
A src/mainboard/cwwk/adl/Kconfig
A src/mainboard/cwwk/adl/Kconfig.name
A src/mainboard/cwwk/adl/Makefile.mk
A src/mainboard/cwwk/adl/board_info.txt
A src/mainboard/cwwk/adl/bootblock.c
A src/mainboard/cwwk/adl/data.vbt
A src/mainboard/cwwk/adl/devicetree.cb
A src/mainboard/cwwk/adl/dsdt.asl
A src/mainboard/cwwk/adl/gpio.h
A src/mainboard/cwwk/adl/mainboard.c
A src/mainboard/cwwk/adl/romstage_fsp_params.c
13 files changed, 521 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81595/11
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Change subject: libpayload: x86: Move Multiboot header to include file
......................................................................
Patch Set 7:
(1 comment)
File payloads/libpayload/arch/x86/multiboot_header.inc:
https://review.coreboot.org/c/coreboot/+/82533/comment/8bc8fec1_d6ee4fd0?us… :
PS7, Line 34: .align 4
> This should not be here since this is included directly into the instruction stream of another funct […]
Acknowledged
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Code-Review+2 by Julius Werner, Verified+1 by build bot (Jenkins)
Change subject: libpayload: x86: Move Multiboot header to include file
......................................................................
libpayload: x86: Move Multiboot header to include file
This moves the multiboot header into its own include file, simplifying
head.S and making it easier to include/exclude the multiboot header
based on config options.
BUG=b:242829490
TEST=Able to build and boot google/rex.
Change-Id: I59a22dfe36044b4dd64a5b028a134be7a7d02a48
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M payloads/libpayload/arch/x86/head.S
A payloads/libpayload/arch/x86/multiboot_header.inc
2 files changed, 58 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/82533/8
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Change subject: mb/google/brox/var/lotso: Update dq map setting
......................................................................
mb/google/brox/var/lotso: Update dq map setting
Based on lotso EVT schematics update dq map settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199
Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/lotso/Makefile.mk
A src/mainboard/google/brox/variants/lotso/memory.c
2 files changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/82600/4
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Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox/var/lotso: Update dq map setting
......................................................................
mb/google/brox/var/lotso: Update dq map setting
Based on lotso EVT schematics update dq map settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Cq-Depend: 82573
Change-Id: I4f03e8a90522cbf2fe06f4160414202dcc4a2199
Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/variants/lotso/Makefile.mk
A src/mainboard/google/brox/variants/lotso/memory.c
2 files changed, 104 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/82600/3
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Change subject: mb/google/brox/var/lotso: Update gpio setting
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82573/comment/16a80d35_59d25457?us… :
PS2, Line 7: gpio and dq map setting
> https://review.coreboot. […]
Done
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