coreboot-gerrit May 2024

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[XS] Change in coreboot[main]: mb/google/brox/var/greenbayupoc: Set power limit values
by Ivan Chen (Code Review) 22 May '24

22 May '24

Attention is currently required from: Garen Wu. Ivan Chen has posted comments on this change by Garen Wu. ( https://review.coreboot.org/c/coreboot/+/82603?usp=email ) Change subject: mb/google/brox/var/greenbayupoc: Set power limit values ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb: https://review.coreboot.org/c/coreboot/+/82603/comment/06513ea7_0136270c?us… : PS1, Line 31: .tdp_pl4 = 45, Should it be only for no battery case rather than the default setting ? -- To view, visit https://review.coreboot.org/c/coreboot/+/82603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaab808ce107251a8a8b96a77c2a636c4117621ba Gerrit-Change-Number: 82603 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 May 2024 07:20:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Update DPTF parameters
by Tony Huang (Code Review) 22 May '24

22 May '24

Attention is currently required from: Sumeet R Pawnikar. Tony Huang has posted comments on this change by Tony Huang. ( https://review.coreboot.org/c/coreboot/+/82434?usp=email ) Change subject: mb/google/rex/var/deku: Update DPTF parameters ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Please help review. Based on test result thermal team decided to keep 65 for passive. -- To view, visit https://review.coreboot.org/c/coreboot/+/82434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Gerrit-Change-Number: 82434 Gerrit-PatchSet: 5 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Wed, 22 May 2024 07:11:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Update DPTF parameters
by Tony Huang (Code Review) 22 May '24

22 May '24

Attention is currently required from: Sumeet R Pawnikar. Hello Derek Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82434?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/var/deku: Update DPTF parameters ...................................................................... mb/google/rex/var/deku: Update DPTF parameters Adjust settings as recommended by thermal team. 1. Update DPTF parameters based on b:308704811#comment4. 2. Adjust PL1 max value from 28W to 33W 3. Set "tcc_offset" to "5" BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/82434/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Gerrit-Change-Number: 82434 Gerrit-PatchSet: 5 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>

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[XS] Change in coreboot[main]: mb/google/brox/var/greenbayupoc: Set power limit values
by Garen Wu (Code Review) 22 May '24

22 May '24

Garen Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82603?usp=email ) Change subject: mb/google/brox/var/greenbayupoc: Set power limit values ...................................................................... mb/google/brox/var/greenbayupoc: Set power limit values Add the RPL CPU power limits and system power limits based on the suggestion of the thermal table. BUG=b:339562639 TEST=emerge-brox coreboot bootimage and boot on DUT Change-Id: Iaab808ce107251a8a8b96a77c2a636c4117621ba Signed-off-by: Wu Garen <wu.garen(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/82603/1 diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index 1939325..cc6b2bc 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -26,6 +26,11 @@ register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl2_override = 30, + .tdp_pl4 = 45, + }" + device domain 0 on device ref igpu on chip drivers/gfx/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/82603?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaab808ce107251a8a8b96a77c2a636c4117621ba Gerrit-Change-Number: 82603 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Jian Tong (Code Review) 22 May '24

22 May '24

Attention is currently required from: Eric Lai, Kun Liu, Paul Menzel, Wentao Qin. Jian Tong has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/82573?usp=email ) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/brox/variants/lotso/gpio.c: https://review.coreboot.org/c/coreboot/+/82573/comment/9ae338e6_1fab60c2?us… : PS9, Line 5: #include <commonlib/helpers.h> > no need. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Gerrit-Change-Number: 82573 Gerrit-PatchSet: 10 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 May 2024 06:44:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Jian Tong (Code Review) 22 May '24

22 May '24

Attention is currently required from: Eric Lai, Jian Tong, Kun Liu, Paul Menzel, Wentao Qin. Hello Eric Lai, Kun Liu, Wentao Qin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82573?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Eric Lai, Code-Review+1 by Wentao Qin, Verified+1 by build bot (Jenkins) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... mb/google/brox/var/lotso: Update gpio setting Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/brox/variants/lotso/Makefile.mk A src/mainboard/google/brox/variants/lotso/gpio.c 2 files changed, 146 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82573/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Gerrit-Change-Number: 82573 Gerrit-PatchSet: 10 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>

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[L] Change in coreboot[main]: libpayload: Add x86_64 (64-bit) support
by Subrata Banik (Code Review) 22 May '24

22 May '24

Attention is currently required from: Arthur Heymans, Julius Werner, Kapil Porwal. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81968?usp=email to look at the new patch set (#70). Change subject: libpayload: Add x86_64 (64-bit) support ...................................................................... libpayload: Add x86_64 (64-bit) support This patch introduces x86_64 (64-bit) support to the payload, building upon the existing x86 (32-bit) architecture. Files necessary for 64-bit compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig option. BUG=b:242829490 TEST=Able to verify all valid combinations between coreboot and payload with this patch. Payload Entry Point Behavior with below code. +----------------+--------------------+----------------------------+ | LP_ARCH_X86_64 | Payload Entry Mode | Description | +----------------+--------------------+----------------------------+ | No | 32-bit | Direct protected mode init | +----------------+--------------------+----------------------------+ | Yes | 32-bit | Protected to long mode | +----------------+--------------------+----------------------------+ | Yes | 64-bit | Long mode initialization | +----------------+--------------------+----------------------------+ Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.mk M payloads/libpayload/arch/x86/Makefile.mk M payloads/libpayload/arch/x86/exception.c A payloads/libpayload/arch/x86/exception_asm_64.S R payloads/libpayload/arch/x86/exec.c M payloads/libpayload/arch/x86/gdb.c A payloads/libpayload/arch/x86/head_64.S M payloads/libpayload/arch/x86/libpayload.ldscript A payloads/libpayload/arch/x86/pt.S M payloads/libpayload/arch/x86/string.c M payloads/libpayload/bin/lpgcc M payloads/libpayload/drivers/storage/ahci_common.c M payloads/libpayload/drivers/usb/uhci.c M payloads/libpayload/include/x86/arch/exception.h M payloads/libpayload/libc/Makefile.mk M payloads/libpayload/vboot/Makefile.mk 18 files changed, 699 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81968/70 -- To view, visit https://review.coreboot.org/c/coreboot/+/81968?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585 Gerrit-Change-Number: 81968 Gerrit-PatchSet: 70 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>

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[M] Change in coreboot[main]: mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting
by Roger Wang (Code Review) 22 May '24

22 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Roger Wang, Shou-Chieh Hsu, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82602?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting ...................................................................... mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting Currently some eMMC can't power on to OS nomally. Use the Intel provides eMMC DLL delay patch to modify some system can't boot to OS problem BUG=b:338887086 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/overridetree.cb 1 file changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82602/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Gerrit-Change-Number: 82602 Gerrit-PatchSet: 2 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Varshit Pandya <15mece14(a)nirmauni.ac.in> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Eric Lai (Code Review) 22 May '24

22 May '24

Attention is currently required from: Jian Tong, Kun Liu, Paul Menzel. Eric Lai has posted comments on this change by Jian Tong. ( https://review.coreboot.org/c/coreboot/+/82573?usp=email ) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/mainboard/google/brox/variants/lotso/gpio.c: https://review.coreboot.org/c/coreboot/+/82573/comment/d03480c1_8a6d7b0a?us… : PS9, Line 5: #include <commonlib/helpers.h> no need. -- To view, visit https://review.coreboot.org/c/coreboot/+/82573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Gerrit-Change-Number: 82573 Gerrit-PatchSet: 9 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 May 2024 06:27:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting
by Roger Wang (Code Review) 22 May '24

22 May '24

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82602?usp=email ) Change subject: mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting ...................................................................... mb/google/nissa/var/sundance: Tuning eMMC DLL delay setting Currently some eMMC can't power on to OS nomally. Use the Intel provides eMMC DLL delay patch to modify some system can't boot to OS problem BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: roger2.wang <roger2.wang(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/overridetree.cb 1 file changed, 46 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/82602/1 diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index bd1ed74..1187062 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -7,52 +7,52 @@ register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" register "PreWake" = "100" - register "sagv" = "SaGv_Enabled" - - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-42.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-42.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-42.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-42.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-42.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-42.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. -- To view, visit https://review.coreboot.org/c/coreboot/+/82602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Gerrit-Change-Number: 82602 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

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coreboot-gerrit May 2024