Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu.
Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81783?usp=email
to look at the new patch set (#4).
Change subject: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
......................................................................
soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and
POSTCAR_STAGE which are used by all Xeon-SP platforms.
After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0
is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X,
POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE.
TEST=Build and boot on intel/archercity CRB
Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/mainboard/bytedance/bd_egs/Kconfig
M src/mainboard/ibm/sbp1/Kconfig
M src/mainboard/intel/archercity_crb/Kconfig
M src/mainboard/intel/cedarisland_crb/Kconfig
M src/mainboard/inventec/transformers/Kconfig
M src/mainboard/ocp/deltalake/Kconfig
M src/mainboard/ocp/tiogapass/Kconfig
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/skx/Kconfig
M src/soc/intel/xeon_sp/spr/Kconfig
10 files changed, 1 insertion(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81783/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/81783?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11
Gerrit-Change-Number: 81783
Gerrit-PatchSet: 4
Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com>
Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com>
Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com>
Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com>
Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>
Gerrit-MessageType: newpatchset
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81800?usp=email )
Change subject: configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms
......................................................................
configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms
This is a good board for compiling TPM PPI sources for the following
reasons (based on `config TPM_PPI` definition):
- uses TPM
- the board is not related to ChromeOS
- ACPI tables are enabled
- it doesn't use EDK2 payload
At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all,
see CB:69161 and CB:81590.
`CONFIG_TPM_PPI` is off by default but at least several configurations
under `configs/` (Protectli, MSI) should exercise the file because they
use EDK2 payload which changes default value. This is however negated
by abuild disabling all payloads and thus effectively preventing
`CONFIG_TPM_PPI` from being set. This board not using EDK2 also ensures
that `CONFIG_TPM_PPI=y` will not disappear after some future
`make savedefconfig`.
Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81800
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
Julius Werner: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
index 4edeb0c..da33450 100644
--- a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
+++ b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms
@@ -1,8 +1,11 @@
# Known-working configuration to boot with TXT enabled. Since BIOS
# and SINIT ACM blobs are missing, use something else as placeholder.
# Used ACMs were extracted from a Supermicro X10SLH firmware update.
+#
+# CONFIG_TPM_PPI=y tests building PPI implementation.
CONFIG_VENDOR_ASROCK=y
CONFIG_BOARD_ASROCK_B85M_PRO4=y
+CONFIG_TPM_PPI=y
CONFIG_TPM2=y
CONFIG_INTEL_TXT=y
CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin"
--
To view, visit https://review.coreboot.org/c/coreboot/+/81800?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7
Gerrit-Change-Number: 81800
Gerrit-PatchSet: 3
Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Attention is currently required from: Kyoung Il Kim, Paul Menzel, Shaunak Saha, srinivas.kulkarni(a)intel.com.
Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81674?usp=email )
Change subject: vc/intel/fsp/mtl: Add Intel Touch Controller UPD in Partial Header
......................................................................
Patch Set 4: Code-Review+1
--
To view, visit https://review.coreboot.org/c/coreboot/+/81674?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I9a18b83fbb2d7760bd58027a4203919489b01580
Gerrit-Change-Number: 81674
Gerrit-PatchSet: 4
Gerrit-Owner: srinivas.kulkarni(a)intel.com
Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com>
Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Shaunak Saha <shaunak.saha(a)intel.com>
Gerrit-Attention: Kyoung Il Kim <kyoung.il.kim(a)intel.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: srinivas.kulkarni(a)intel.com
Gerrit-Comment-Date: Wed, 10 Apr 2024 07:14:46 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment