coreboot-gerrit April 2024

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#43). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=Build and boot on intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/chipset.cb A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 25 files changed, 1,274 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 43 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81783?usp=email to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 ...................................................................... soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. TEST=Build and boot on intel/archercity CRB Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/mainboard/bytedance/bd_egs/Kconfig M src/mainboard/ibm/sbp1/Kconfig M src/mainboard/intel/archercity_crb/Kconfig M src/mainboard/intel/cedarisland_crb/Kconfig M src/mainboard/inventec/transformers/Kconfig M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/tiogapass/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 10 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81783/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Gerrit-Change-Number: 81783 Gerrit-PatchSet: 4 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: tree: Drop unused <edid.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81821?usp=email ) Change subject: tree: Drop unused <edid.h> ...................................................................... tree: Drop unused <edid.h> Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/aspeed/ast2050/ast2050.c M src/mainboard/google/corsola/panel.c M src/mainboard/google/geralt/panel.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_rialto/mainboard.c M src/soc/mediatek/common/ddp.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/dsi.c M src/soc/qualcomm/sc7180/display/dsi_phy_pll.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c 11 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/81821/1 diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index ea86e28..6ceb820 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> -#include <edid.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c index 01eb243..e77cb97 100644 --- a/src/mainboard/google/corsola/panel.c +++ b/src/mainboard/google/corsola/panel.c @@ -3,7 +3,6 @@ #include <boardid.h> #include <cbfs.h> #include <device/i2c_simple.h> -#include <edid.h> #include <gpio.h> #include <soc/ddp.h> #include <soc/dsi.h> diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index 9bf7416..82f49ab 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -4,7 +4,6 @@ #include <cbfs.h> #include <console/console.h> #include <delay.h> -#include <edid.h> #include <gpio.h> #include <identity.h> #include <soc/gpio_common.h> diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 7d17bcc..0206e6d 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -5,7 +5,6 @@ #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> -#include <edid.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index 1233248..8addc39 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -4,7 +4,6 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <device/i2c_simple.h> -#include <edid.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 4551515..f3fdc21 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/device.h> #include <device/i2c_simple.h> -#include <edid.h> #include <gpio.h> #include <soc/display.h> #include <soc/grf.h> diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 7e2d373..a4c9696 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> -#include <edid.h> #include <soc/addressmap.h> #include <soc/ddp.h> #include <types.h> diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 5935d0d..227be44 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> -#include <edid.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c index b9bbea3..fc4fd7b 100644 --- a/src/soc/nvidia/tegra210/dsi.c +++ b/src/soc/nvidia/tegra210/dsi.c @@ -8,7 +8,6 @@ #include <soc/addressmap.h> #include <soc/clock.h> #include <device/device.h> -#include <edid.h> #include <soc/nvidia/tegra/types.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c index 1fcfb79..653e55b 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy_pll.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <stdint.h> -#include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> #include <soc/display/dsi_phy_pll.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index 5b36c4b..eee2ef7 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <device/mmio.h> -#include <edid.h> #include <soc/clock.h> #include <soc/display/edp_reg.h> #include <soc/display/edp_phy.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66265727b68b6ad10722439314b466298dbfff28 Gerrit-Change-Number: 81821 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: tree: drop unused <halt.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81820?usp=email ) Change subject: tree: drop unused <halt.h> ...................................................................... tree: drop unused <halt.h> Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/ec/starlabs/merlin/ite.c M src/lib/halt.c M src/soc/mediatek/mt8186/rtc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81820/1 diff --git a/src/ec/starlabs/merlin/ite.c b/src/ec/starlabs/merlin/ite.c index 8acbbc7..2574a60 100644 --- a/src/ec/starlabs/merlin/ite.c +++ b/src/ec/starlabs/merlin/ite.c @@ -6,7 +6,6 @@ #include <ec/acpi/ec.h> #include <option.h> #include <pc80/keyboard.h> -#include <halt.h> #include "ec.h" #include "ecdefs.h" diff --git a/src/lib/halt.c b/src/lib/halt.c index 441f5bb..d28a19c 100644 --- a/src/lib/halt.c +++ b/src/lib/halt.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/hlt.h> -#include <halt.h> void __noreturn abort(void) { diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c index 7375bc3..056c65c 100644 --- a/src/soc/mediatek/mt8186/rtc.c +++ b/src/soc/mediatek/mt8186/rtc.c @@ -6,7 +6,6 @@ */ #include <delay.h> -#include <halt.h> #include <soc/rtc.h> #include <soc/rtc_common.h> #include <soc/mt6366.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7394882..c5cbb40 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/pci_ids.h> #include <elog.h> -#include <halt.h> #include <option.h> #include <southbridge/intel/common/me.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 8702c4d..f5c791b 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -18,7 +18,6 @@ #include <device/pci_ids.h> #include <string.h> #include <elog.h> -#include <halt.h> #include <option.h> #include <southbridge/intel/common/me.h> diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 2db3c2d..7c098cc 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -8,7 +8,6 @@ #include <device/pci_ids.h> #include <string.h> #include <delay.h> -#include <halt.h> #include <timer.h> #include "me.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/81820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Gerrit-Change-Number: 81820 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: tree: Drop unused <stdlib.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81819?usp=email ) Change subject: tree: Drop unused <stdlib.h> ...................................................................... tree: Drop unused <stdlib.h> Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/efi/efivars.c M src/drivers/efi/option.c M src/drivers/usb/hub/acpi.c M src/lib/bootsplash.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/iio_ioapic.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/mediatek/common/early_init.c M src/soc/mediatek/mt8195/pcie.c M src/soc/qualcomm/sc7280/display/edp_ctrl.c M src/superio/nuvoton/npcd378/superio.c 12 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81819/1 diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c index e7eabf4..ea8ab99 100644 --- a/src/drivers/efi/efivars.c +++ b/src/drivers/efi/efivars.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <console/console.h> diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c index 8e5b326..d634c96 100644 --- a/src/drivers/efi/option.c +++ b/src/drivers/efi/option.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdlib.h> #include <option.h> #include <smmstore.h> diff --git a/src/drivers/usb/hub/acpi.c b/src/drivers/usb/hub/acpi.c index 3944952..ebbe4b2 100644 --- a/src/drivers/usb/hub/acpi.c +++ b/src/drivers/usb/hub/acpi.c @@ -2,7 +2,6 @@ #include <acpi/acpigen.h> #include <acpi/acpi_device.h> -#include <stdlib.h> #include "chip.h" diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 0512770..38d0ce7 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <endian.h> #include <bootsplash.h> -#include <stdlib.h> #include "jpeg.h" diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index aabc54d..a2de2d4 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -9,7 +9,6 @@ #include <soc/chip_common.h> #include <soc/soc_util.h> #include <soc/util.h> -#include <stdlib.h> /** * Find all device of a given vendor and type for the specified socket. diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 7e831ab..143cc89 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -12,7 +12,6 @@ #include <soc/chip_common.h> #include <soc/soc_util.h> #include <soc/util.h> -#include <stdlib.h> static const STACK_RES *domain_to_stack_res(const struct device *dev) { diff --git a/src/soc/intel/xeon_sp/iio_ioapic.c b/src/soc/intel/xeon_sp/iio_ioapic.c index 3a99477..66b827f 100644 --- a/src/soc/intel/xeon_sp/iio_ioapic.c +++ b/src/soc/intel/xeon_sp/iio_ioapic.c @@ -5,7 +5,6 @@ #include <soc/chip_common.h> #include <soc/util.h> #include <stdint.h> -#include <stdlib.h> static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1]; diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 83418dc..9ad09f4 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -10,7 +10,6 @@ #include <soc/pci_devs.h> #include <soc/soc_util.h> #include <soc/util.h> -#include <stdlib.h> #include <pc80/mc146818rtc.h> const EWL_PRIVATE_DATA *get_ewl_hob(void) diff --git a/src/soc/mediatek/common/early_init.c b/src/soc/mediatek/common/early_init.c index 55ba447..0587802 100644 --- a/src/soc/mediatek/common/early_init.c +++ b/src/soc/mediatek/common/early_init.c @@ -2,7 +2,6 @@ #include <assert.h> #include <soc/early_init.h> -#include <stdlib.h> #include <string.h> static struct early_init_data *find_early_init(void) diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 960d0bb..eb7ad87 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -7,7 +7,6 @@ #include <soc/early_init.h> #include <soc/pcie.h> #include <soc/pcie_common.h> -#include <stdlib.h> #define PCIE_REG_BASE_PORT0 0x112f0000 #define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c index 2bf7958..48a832a 100644 --- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c +++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c @@ -7,7 +7,6 @@ #include <delay.h> #include <types.h> #include <string.h> -#include <stdlib.h> #include <soc/clock.h> #include <gpio.h> #include <soc/display/edp_reg.h> diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index ddf63cd..d642dd5 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -10,7 +10,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <superio/common/ssdt.h> -#include <stdlib.h> #include "npcd378.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/81819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7e36cfa5a09d94bb58f12f9bd262255a630424c Gerrit-Change-Number: 81819 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: tree: Drop unused <string.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81818?usp=email ) Change subject: tree: Drop unused <string.h> ...................................................................... tree: Drop unused <string.h> Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/commonlib/storage/pci_sdhci.c M src/drivers/amd/agesa/s3_mtrr.c M src/drivers/efi/option.c M src/drivers/ipmi/ocp/ipmi_sel.c M src/drivers/sof/sof.c M src/mainboard/google/geralt/panel.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/starlabs/lite/variants/glk/gpio.c M src/mainboard/starlabs/lite/variants/glkr/gpio.c M src/mainboard/starlabs/starbook/variants/cml/romstage.c M src/northbridge/intel/gm45/iommu.c M src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c M src/soc/amd/mendocino/fsp_misc_data_hob.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/mediatek/mt8195/pcie.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3399/clock.c 20 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81818/1 diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index de9dd1b..f7922d4 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -4,7 +4,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <string.h> #include "sd_mmc.h" #include "storage.h" diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 51e8a4d..b085b4d 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -6,7 +6,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> -#include <string.h> #include <northbridge/amd/agesa/agesa_helper.h> /* TODO: Do we want MTRR_DEF_TYPE_MSR too? */ diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c index 3960cfc..8e5b326 100644 --- a/src/drivers/efi/option.c +++ b/src/drivers/efi/option.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdlib.h> -#include <string.h> #include <option.h> #include <smmstore.h> diff --git a/src/drivers/ipmi/ocp/ipmi_sel.c b/src/drivers/ipmi/ocp/ipmi_sel.c index f7605ec..157bdbd 100644 --- a/src/drivers/ipmi/ocp/ipmi_sel.c +++ b/src/drivers/ipmi/ocp/ipmi_sel.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_if.h> -#include <string.h> #include "ipmi_ocp.h" diff --git a/src/drivers/sof/sof.c b/src/drivers/sof/sof.c index db945aa..8cd577e 100644 --- a/src/drivers/sof/sof.c +++ b/src/drivers/sof/sof.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/path.h> -#include <string.h> #include "chip.h" diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index 3f55cac..9bf7416 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -11,7 +11,6 @@ #include <soc/i2c.h> #include <soc/pmif.h> #include <soc/regulator.h> -#include <string.h> #include "gpio.h" #include "panel.h" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 00d94e6..b525a0b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <string.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/starlabs/lite/variants/glk/gpio.c b/src/mainboard/starlabs/lite/variants/glk/gpio.c index f24ed9e..321082c 100644 --- a/src/mainboard/starlabs/lite/variants/glk/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glk/gpio.c @@ -3,7 +3,6 @@ #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include <string.h> #include <variants.h> #include <types.h> diff --git a/src/mainboard/starlabs/lite/variants/glkr/gpio.c b/src/mainboard/starlabs/lite/variants/glkr/gpio.c index 11a7d31..41d2b47 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glkr/gpio.c @@ -3,7 +3,6 @@ #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include <string.h> #include <variants.h> #include <types.h> diff --git a/src/mainboard/starlabs/starbook/variants/cml/romstage.c b/src/mainboard/starlabs/starbook/variants/cml/romstage.c index 75a19e5..372f8b0 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/cml/romstage.c @@ -5,7 +5,6 @@ #include <option.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> -#include <string.h> #include <types.h> static unsigned int get_memory_config_straps(void) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4f6e000..6a68dff 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <string.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c b/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c index 6e615dd..aaf492e 100644 --- a/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c +++ b/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <FspGuids.h> #include <fsp/util.h> -#include <string.h> #include <types.h> diff --git a/src/soc/amd/mendocino/fsp_misc_data_hob.c b/src/soc/amd/mendocino/fsp_misc_data_hob.c index ed35800..e5eae02 100644 --- a/src/soc/amd/mendocino/fsp_misc_data_hob.c +++ b/src/soc/amd/mendocino/fsp_misc_data_hob.c @@ -5,7 +5,6 @@ #include <fsp/amd_misc_data.h> #include <fsp/amd_misc_data_hob.h> #include <fsp/util.h> -#include <string.h> #include <types.h> static enum cb_err get_amd_misc_data_hob(const struct amd_misc_data **fsp_misc_data, int min_revision) diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index ca4e5e1..c8d1978 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -20,7 +20,6 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> -#include <string.h> #include <types.h> /* diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 6ed018c..83418dc 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -11,7 +11,6 @@ #include <soc/soc_util.h> #include <soc/util.h> #include <stdlib.h> -#include <string.h> #include <pc80/mc146818rtc.h> const EWL_PRIVATE_DATA *get_ewl_hob(void) diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 7f60d68..960d0bb 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -8,7 +8,6 @@ #include <soc/pcie.h> #include <soc/pcie_common.h> #include <stdlib.h> -#include <string.h> #define PCIE_REG_BASE_PORT0 0x112f0000 #define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index a2dda39..9d330a6 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -5,7 +5,6 @@ #include <edid.h> #include <timer.h> #include <types.h> -#include <string.h> #include <soc/display/edp_aux.h> #include <soc/display/edp_reg.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index 5074317..5b36c4b 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -6,7 +6,6 @@ #include <soc/clock.h> #include <soc/display/edp_reg.h> #include <soc/display/edp_phy.h> -#include <string.h> #include <timer.h> static void edp_phy_ssc_en(bool en) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index c3a9ac2..b6960aa 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -12,7 +12,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <string.h> struct pll_div { u32 nr; diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 115d289..0b027ed 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -11,7 +11,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <string.h> struct pll_div { u32 refdiv; -- To view, visit https://review.coreboot.org/c/coreboot/+/81818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Gerrit-Change-Number: 81818 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Disable external fivr
by Eric Lai (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Ian Feng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81607?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable external fivr ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60 Gerrit-Change-Number: 81607 Gerrit-PatchSet: 7 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Apr 2024 07:31:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms
by Felix Held (Code Review) 10 Apr '24

10 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81800?usp=email ) Change subject: configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms ...................................................................... configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms This is a good board for compiling TPM PPI sources for the following reasons (based on `config TPM_PPI` definition): - uses TPM - the board is not related to ChromeOS - ACPI tables are enabled - it doesn't use EDK2 payload At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all, see CB:69161 and CB:81590. `CONFIG_TPM_PPI` is off by default but at least several configurations under `configs/` (Protectli, MSI) should exercise the file because they use EDK2 payload which changes default value. This is however negated by abuild disabling all payloads and thus effectively preventing `CONFIG_TPM_PPI` from being set. This board not using EDK2 also ensures that `CONFIG_TPM_PPI=y` will not disappear after some future `make savedefconfig`. Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81800 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms index 4edeb0c..da33450 100644 --- a/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms +++ b/configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms @@ -1,8 +1,11 @@ # Known-working configuration to boot with TXT enabled. Since BIOS # and SINIT ACM blobs are missing, use something else as placeholder. # Used ACMs were extracted from a Supermicro X10SLH firmware update. +# +# CONFIG_TPM_PPI=y tests building PPI implementation. CONFIG_VENDOR_ASROCK=y CONFIG_BOARD_ASROCK_B85M_PRO4=y +CONFIG_TPM_PPI=y CONFIG_TPM2=y CONFIG_INTEL_TXT=y CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/cpu/intel/stm/stm.bin" -- To view, visit https://review.coreboot.org/c/coreboot/+/81800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7 Gerrit-Change-Number: 81800 Gerrit-PatchSet: 3 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Disable external fivr
by Sumeet R Pawnikar (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Ian Feng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81607?usp=email ) Change subject: mb/google/nissa/var/craaskov: Disable external fivr ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9280a86bf78caa10b527a6569ac580dfe1d66f60 Gerrit-Change-Number: 81607 Gerrit-PatchSet: 7 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Apr 2024 07:19:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
by Sumeet R Pawnikar (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Karthik Ramasubramanian, Shelley Chen. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81789?usp=email ) Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81789/comment/29ab8295_bfe3a036 : PS3, Line 9: Remove extra space. -- To view, visit https://review.coreboot.org/c/coreboot/+/81789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7 Gerrit-Change-Number: 81789 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Apr 2024 07:16:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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