coreboot-gerrit April 2024

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

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[XS] Change in coreboot[main]: tree: Drop unused <timer.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81822?usp=email ) Change subject: tree: Drop unused <timer.h> ...................................................................... tree: Drop unused <timer.h> Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c M src/soc/intel/meteorlake/finalize.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81822/1 diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c index f47da22..bb9d10a 100644 --- a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c +++ b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c @@ -16,7 +16,6 @@ #include <spi_sdcard.h> #include <stdint.h> #include <symbols.h> -#include <timer.h> // There are two different means of accessing the SPI flash. // They are controlled by the fctrl register. diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 64beb85..ed29ba9 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -22,7 +22,6 @@ #include <soc/smbus.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> -#include <timer.h> static void pch_handle_sideband(config_t *config) { -- To view, visit https://review.coreboot.org/c/coreboot/+/81822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib454330c5f584760c47ff0127a720cec5773b922 Gerrit-Change-Number: 81822 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: tree: Drop unused <halt.h>
by Elyes Haouas (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Elyes Haouas, Hung-Te Lin, Sean Rhodes, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Sean Rhodes, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81820?usp=email to look at the new patch set (#3). Change subject: tree: Drop unused <halt.h> ...................................................................... tree: Drop unused <halt.h> Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/ec/starlabs/merlin/ite.c M src/soc/mediatek/mt8186/rtc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81820/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Gerrit-Change-Number: 81820 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc: Update GCC from 13.2 to 14-20240407
by Felix Singer (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Hello Elyes Haouas, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81683?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review-1 by Elyes Haouas, Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Update GCC from 13.2 to 14-20240407 ...................................................................... util/crossgcc: Update GCC from 13.2 to 14-20240407 Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/gcc-14-20240407_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240407_gnat.patch R util/crossgcc/patches/gcc-14-20240407_libcpp.patch R util/crossgcc/patches/gcc-14-20240407_libgcc.patch R util/crossgcc/patches/gcc-14-20240407_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240407_rv32iafc.patch D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240407.tar.xz.cksum 9 files changed, 11 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81683/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf5912d1fcdfabab7fe006b7e0cd4ebd25c07d09 Gerrit-Change-Number: 81683 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
by Lean Sheng Tan (Code Review) 10 Apr '24

10 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81783?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 ...................................................................... soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. TEST=Build and boot on intel/archercity CRB Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81783 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/bytedance/bd_egs/Kconfig M src/mainboard/ibm/sbp1/Kconfig M src/mainboard/intel/archercity_crb/Kconfig M src/mainboard/intel/cedarisland_crb/Kconfig M src/mainboard/inventec/transformers/Kconfig M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/tiogapass/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 10 files changed, 1 insertion(+), 19 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/bytedance/bd_egs/Kconfig b/src/mainboard/bytedance/bd_egs/Kconfig index 4293181..433d962 100644 --- a/src/mainboard/bytedance/bd_egs/Kconfig +++ b/src/mainboard/bytedance/bd_egs/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig index d56f301..cb5b3fd 100644 --- a/src/mainboard/ibm/sbp1/Kconfig +++ b/src/mainboard/ibm/sbp1/Kconfig @@ -8,7 +8,6 @@ select IPMI_KCS select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select HAVE_ACPI_TABLES select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/intel/archercity_crb/Kconfig b/src/mainboard/intel/archercity_crb/Kconfig index 87f274b..200fa49 100644 --- a/src/mainboard/intel/archercity_crb/Kconfig +++ b/src/mainboard/intel/archercity_crb/Kconfig @@ -11,7 +11,6 @@ select IPMI_OCP select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig b/src/mainboard/intel/cedarisland_crb/Kconfig index 034ca3b..4e3a1cc 100644 --- a/src/mainboard/intel/cedarisland_crb/Kconfig +++ b/src/mainboard/intel/cedarisland_crb/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/inventec/transformers/Kconfig b/src/mainboard/inventec/transformers/Kconfig index d0fdb82..108bf43 100644 --- a/src/mainboard/inventec/transformers/Kconfig +++ b/src/mainboard/inventec/transformers/Kconfig @@ -11,7 +11,6 @@ select IPMI_KCS_ROMSTAGE select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 039e6f9..27c8c34 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -7,7 +7,6 @@ select BOARD_ROMSIZE_KB_65536 select CONSOLE_OVERRIDE_LOGLEVEL select HAVE_ACPI_TABLES - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select IPMI_KCS diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 886743c..cbfb5c8 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -9,7 +9,6 @@ select IPMI_KCS select IPMI_KCS_ROMSTAGE select IPMI_OCP - select MAINBOARD_USES_FSP2_0 select OCP_DMI select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 78227ed..51f407e 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -45,15 +45,10 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select POSTCAR_STAGE if XEON_SP_COMMON_BASE -config MAINBOARD_USES_FSP2_0 - bool - default y - select PLATFORM_USES_FSP2_0 - select POSTCAR_STAGE - config MAX_SOCKET int default 2 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 4a9e683..25e35bd 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -11,13 +11,8 @@ if SOC_INTEL_SKYLAKE_SP -config MAINBOARD_USES_FSP2_0 - bool - default y - config FSP_HEADER_PATH string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" config MAX_SOCKET diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 2e0ad01..b40a534 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -28,7 +28,6 @@ config FSP_HEADER_PATH string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp" config MAX_CPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/81783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Gerrit-Change-Number: 81783 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Arthur Heymans, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Nicholas Chin, Patrick Rudolph, Paul Menzel, TangYiwei, Varshit Pandya. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81319?usp=email ) Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City ...................................................................... Patch Set 32: (7 comments) File src/mainboard/intel/avenuecity_crb/bootblock.c: https://review.coreboot.org/c/coreboot/+/81319/comment/71be718a_bb88a90d : PS31, Line 5: #include <device/pci_def.h> : #include <device/pci_ops.h> > unused? Done https://review.coreboot.org/c/coreboot/+/81319/comment/f5401f8a_54a8779c : PS31, Line 9: #include <soc/pci_devs.h> > unused? Done https://review.coreboot.org/c/coreboot/+/81319/comment/23beaa1d_67f1443b : PS31, Line 21: CONFIG_ASPEED_SIO_PORT > Does this need to be a Kconfig? Done File src/mainboard/intel/avenuecity_crb/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81319/comment/6f13a390_983d363a : PS31, Line 16: register "gen2_dec" = "0x0" : register "gen3_dec" = "0x0" : register "gen4_dec" = "0x0" > 0 is default so no need to set it explicitly Done https://review.coreboot.org/c/coreboot/+/81319/comment/2e9117e4_5386fcb3 : PS31, Line 21: register "serial_io_uart_debug_io_base" = "0x3F8" > Can't CONFIG_TTYS0_BASE be reused? The devicetree.cb cannot directly refer to a config macro and cannot update at the moment. Will check if there is method to add the support. File src/mainboard/intel/avenuecity_crb/include/config/iio.h: https://review.coreboot.org/c/coreboot/+/81319/comment/95a384d8_6db31df9 : PS31, Line 12: _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), > suggestion: It looks like slots are either: […] In this basic example it should be no problem. But I checked the full configuration cases, others fields also needs to be set to enable some further features hence the full configuration macros still needs to be kept. I tried to optimize a bit. Not sure if this is better. https://review.coreboot.org/c/coreboot/+/81319/comment/62ff15a4_5a57d3d0 : PS31, Line 8: static const iio_pe_config avc_iio_config_table[] = { : {_IIO_PE_CFG_STRUCT(0x0, PE0, IIO_BIFURCATE_x2x2x2x2x8, PE_TYPE_PCIE) { : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x1), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x2), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x3), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x4), : _IIO_PORT_CFG_STRUCT(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, : 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x4B, 0x5) : }}, : }; : > move to romstage.c file? Data structures in a header is not a good idea. I see. I move the avenuecity_crb/include/config/iio.h to avenuecity_crb/config/iio.c and update Makefile to include it. We have some future config tables which could be put into config/xxx.c as well. Your opinion? -- To view, visit https://review.coreboot.org/c/coreboot/+/81319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Gerrit-Change-Number: 81319 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Wed, 10 Apr 2024 10:41:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81318?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... Patch Set 32: (4 comments) File src/soc/intel/xeon_sp/gnr/include/soc/iio.h: https://review.coreboot.org/c/coreboot/+/81318/comment/65554fbc_df6ea9c8 : PS31, Line 12: typedef > Coding style does not allow typedefs for structs. Done https://review.coreboot.org/c/coreboot/+/81318/comment/f7c112ea_8a098ec5 : PS31, Line 88: rsv1, rsv2, rsv3, rsv4, > what are these? These are some configuration knobs which will be published after SoC launch, at the moment, we have to keep them as reserved. https://review.coreboot.org/c/coreboot/+/81318/comment/6e7cf35e_99d906cd : PS31, Line 92: vaddr > Add () around each argument Done File src/soc/intel/xeon_sp/gnr/soc_iio.c: https://review.coreboot.org/c/coreboot/+/81318/comment/c87e2458_27405944 : PS31, Line 23: memset(&iio_upd_hob, 0, sizeof(iio_upd_hob)); > the static initialization is already 0 by default Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 10 Apr 2024 10:38:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 42: (6 comments) File src/soc/intel/xeon_sp/gnr/Kconfig: https://review.coreboot.org/c/coreboot/+/81316/comment/1a306075_3db3e197 : PS42, Line 113: config INTEL_TXT_SINIT_SIZE : hex : default 0x50000 : help : According to document number 572782 this needs to be 256KiB : for the SINIT module and 64KiB for SINIT data. : : config INTEL_TXT_HEAP_SIZE : hex : default 0xf0000 : help : This must be 960KiB according to 572782. > Is CBnT/TXT validated? If not I'd just remove this as it might give a false impression. Done File src/soc/intel/xeon_sp/gnr/chip.c: https://review.coreboot.org/c/coreboot/+/81316/comment/1d213ab7_e80b08b0 : PS42, Line 48: cpu_bus_ops > can also be hooked up directly in devicetree. Done https://review.coreboot.org/c/coreboot/+/81316/comment/f8fd2ac0_032e9751 : PS42, Line 55: dev->ops = &hpet_device_ops; > I'd recommend a chipset.cb file which hooks up this ops. Done https://review.coreboot.org/c/coreboot/+/81316/comment/093de309_b8767f90 : PS42, Line 84: .final = chip_final, > Why have a function pointer to nothing? Done File src/soc/intel/xeon_sp/gnr/romstage.c: https://review.coreboot.org/c/coreboot/+/81316/comment/eba617e0_336e50fb : PS42, Line 20: void __weak mainboard_memory_init_params(FSPM_UPD *mupd) : { : /* Default weak implementation */ : } > Is doing nothing valid on any board? If not I'd rather have the build fails and make it mandatory fo […] Done File src/soc/intel/xeon_sp/gnr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/81316/comment/999c2db7_8f006d6f : PS42, Line 47: nsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) : { : struct device *cpu; : uint8_t num_cpus = 0; : : for (cpu = all_devices; cpu; cpu = cpu->next) { : if ((cpu->path.type != DEVICE_PATH_APIC) || : (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { : continue; : } : if (!cpu->enabled) : continue; : current += acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id); : num_cpus++; : } : : return current; : } > I don't see a call to this (neither on SPR-SP). […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 42 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 10 Apr 2024 10:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Nicholas Chin, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Varshit Pandya. Hello Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81319?usp=email to look at the new patch set (#32). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City ...................................................................... mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP AP SoCs (Granite Rapids AP and Sierra Forest AP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- A configs/builder/config.intel.crb.avc A src/mainboard/intel/avenuecity_crb/Kconfig A src/mainboard/intel/avenuecity_crb/Kconfig.name A src/mainboard/intel/avenuecity_crb/Makefile.mk A src/mainboard/intel/avenuecity_crb/board.fmd A src/mainboard/intel/avenuecity_crb/board_info.txt A src/mainboard/intel/avenuecity_crb/bootblock.c A src/mainboard/intel/avenuecity_crb/config/iio.c A src/mainboard/intel/avenuecity_crb/devicetree.cb A src/mainboard/intel/avenuecity_crb/dsdt.asl A src/mainboard/intel/avenuecity_crb/ramstage.c A src/mainboard/intel/avenuecity_crb/romstage.c 12 files changed, 271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/81319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Gerrit-Change-Number: 81319 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 10 Apr '24

10 Apr '24

Attention is currently required from: Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81318?usp=email to look at the new patch set (#32). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... soc/intel/xeon_sp/gnr: Add IIO config utils Add IIO configuration utils shared in GNR boards to handle the complex IIO configuration settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/include/soc/iio.h A src/soc/intel/xeon_sp/gnr/soc_iio.c 3 files changed, 195 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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