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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69162?usp=email )
Change subject: security/tpm: support compiling in multiple TPM drivers
......................................................................
Patch Set 38:
(3 comments)
File src/drivers/crb/tis.h:
PS38:
nit: rather than making new headers everywhere I think these could also just go into the various tpm.h that exist already.
File src/lib/program.ld:
https://review.coreboot.org/c/coreboot/+/69162/comment/3fec1ef4_e78c1698 :
PS37, Line 46: RECORD_SIZE(tis_drivers)
> I don't have strong preference here, changed to a sequence of `if`s. […]
I think as long as all we're hardcoding there is "this driver exists", that's fine.
File src/security/tpm/tss/tss.c:
https://review.coreboot.org/c/coreboot/+/69162/comment/334c4f51_7c1d1fd5 :
PS38, Line 36: DRIVER_TIS_DEFAULT
I don't think this is correct for the Atmel case? I think `CONFIG(I2C_TPM)` is the right one to cover them both.
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Change subject: Makefile.mk: Account for large code model sections in cbfs_struct
......................................................................
Patch Set 4: Code-Review+2
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Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brox/variants/baseboard/brox/gpio.c:
https://review.coreboot.org/c/coreboot/+/81789/comment/bab00ed8_0a648265 :
PS5, Line 202: PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2),
Question: Should we have to use this always or should it be used only when ISH in full sensing mode?
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Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81827?usp=email )
Change subject: mb/dell/optiplex_9020: Add support for TPM1.2 device
......................................................................
mb/dell/optiplex_9020: Add support for TPM1.2 device
These machines come with a TPM1.2 device by default. It is somewhat
obsolote these days, but there is no harm in enabling it.
Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
M src/mainboard/dell/optiplex_9020/Kconfig
M src/mainboard/dell/optiplex_9020/devicetree.cb
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/81827/1
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
index 2de4a9a..38c3281 100644
--- a/src/mainboard/dell/optiplex_9020/Kconfig
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -12,7 +12,9 @@
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
+ select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
index dce5869..841285b 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -70,6 +70,9 @@
device pnp 2e.b off end # Floppy Controller
device pnp 2e.11 off end # Parallel Port
end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
end
device pci 1f.2 on end # SATA controller 1
device pci 1f.3 on end # SMBus
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/dell/optiplex_9020: Implement late HWM initialization
......................................................................
mb/dell/optiplex_9020: Implement late HWM initialization
There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.
The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 0.
Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.
This was tested to make fan control work on my OptiPlex 7020 SFF.
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
M src/mainboard/dell/optiplex_9020/Makefile.mk
M src/mainboard/dell/optiplex_9020/bootblock.c
M src/mainboard/dell/optiplex_9020/cmos.default
M src/mainboard/dell/optiplex_9020/cmos.layout
M src/mainboard/dell/optiplex_9020/mainboard.c
A src/mainboard/dell/optiplex_9020/sch5555_ec.c
A src/mainboard/dell/optiplex_9020/sch5555_ec.h
7 files changed, 454 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/81529/5
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Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81789/comment/5424a3b6_1160c25b :
PS3, Line 9:
> Remove extra space.
Done
https://review.coreboot.org/c/coreboot/+/81789/comment/8190fe3f_08c42c79 :
PS3, Line 10: and
> be an
Done
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Change subject: mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
......................................................................
mb/google/brox: Initialize NOTE_BOOK_MODE GPIO
The GPIO for NOTE_BOOK_MODE has changed from GPP_B17 to GPP_E9. Also
initializing NOTE_BOOT_MODE to be an output GPIO.
BUG=b:316421831
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
Make sure that brox device still boots up with this change.
Change-Id: I4a091b58deb855c7a7f1489a9506db2f821503b7
Signed-off-by: Shelley Chen <shchen(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/gpio.c
1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81789/4
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