coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Add support for TPM1.2 device
by Máté Kukri (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Máté Kukri. Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81827?usp=email to look at the new patch set (#2). Change subject: mb/dell/optiplex_9020: Add support for TPM1.2 device ...................................................................... mb/dell/optiplex_9020: Add support for TPM1.2 device These machines come with a TPM1.2 device by default. It is somewhat obsolete these days, but there is no harm in enabling it. Change-Id: Iec05321862aed58695c256b00494e5953219786d Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> --- M src/mainboard/dell/optiplex_9020/Kconfig M src/mainboard/dell/optiplex_9020/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/81827/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec05321862aed58695c256b00494e5953219786d Gerrit-Change-Number: 81827 Gerrit-PatchSet: 2 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Fix SATA port maps
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Arthur Heymans, Felix Singer, Máté Kukri, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81550?usp=email ) Change subject: mb/dell/optiplex_9020: Fix SATA port maps ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81550/comment/b34eb584_237559ec : PS3, Line 9: Previously incorrect sets of SATA ports were enabled. If unsure, I think there's no harm in just enabling all six ports. -- To view, visit https://review.coreboot.org/c/coreboot/+/81550?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32cb236b8f8140fba4a04c23161363d21741dcbc Gerrit-Change-Number: 81550 Gerrit-PatchSet: 3 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:29:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/device/device.h: Drop duplicated <console/console.h>
by Elyes Haouas (Code Review) 11 Apr '24

11 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81828?usp=email ) Change subject: include/device/device.h: Drop duplicated <console/console.h> ...................................................................... include/device/device.h: Drop duplicated <console/console.h> Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/device/device.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/81828/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 32a838d..49b4003 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -242,7 +242,6 @@ /* Debug macros */ #if CONFIG(DEBUG_FUNC) -#include <console/console.h> #define DEV_FUNC_ENTER(dev) \ printk(BIOS_SPEW, "%s:%s:%d: ENTER (dev: %s)\n", \ __FILE__, __func__, __LINE__, dev_path(dev)) -- To view, visit https://review.coreboot.org/c/coreboot/+/81828?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib81c81843a5252e2ead9ce175cea2fa42f0e8152 Gerrit-Change-Number: 81828 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/dell/optiplex_9020: Add support for TPM1.2 device
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Máté Kukri. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81827?usp=email ) Change subject: mb/dell/optiplex_9020: Add support for TPM1.2 device ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81827/comment/286510ff_34af1b51 : PS1, Line 10: obsolote typo: obsolete https://review.coreboot.org/c/coreboot/+/81827/comment/06ea447d_e93e71e4 : PS1, Line 10: obsolote these days, but there is no harm in enabling it. Has this been tested? -- To view, visit https://review.coreboot.org/c/coreboot/+/81827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iec05321862aed58695c256b00494e5953219786d Gerrit-Change-Number: 81827 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:28:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use official microcodes
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81637?usp=email ) Change subject: soc/intel/xeon_sp/spr: Use official microcodes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Gerrit-Change-Number: 81637 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:26:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include: Add 'IWYU pragma: export' comment
by Elyes Haouas (Code Review) 11 Apr '24

11 Apr '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81824?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: include: Add 'IWYU pragma: export' comment ...................................................................... include: Add 'IWYU pragma: export' comment This pragma says to IWYU (Include What You Use) that the current file is supposed to provide commented header. Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/device/device.h M src/include/timestamp.h 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81824/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3acb5e6b18443e454d8174b0b1f9d207c0fb78b5 Gerrit-Change-Number: 81824 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop microcode constraints
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Ray Ni, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81635?usp=email ) Change subject: soc/intel/xeon_sp/spr: Drop microcode constraints ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS1: > > Is FSP-T used for this platform? […] Sounds good -- To view, visit https://review.coreboot.org/c/coreboot/+/81635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Gerrit-Change-Number: 81635 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:26:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Compress FSP-S
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Ray Ni, Shuo Liu, Sumeet R Pawnikar, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email ) Change subject: soc/intel/xeon_sp: Compress FSP-S ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81634/comment/ab02f3d2_27da6782 : PS1, Line 12: Test: Still boots on ibm/sbp1. > > Per our check, the LZ4 decompression cost usually <1s, which should be acceptable in a server boot […] Boot time differences when using a debug FSP-S would be rather meaningless (most of the time would be spent spamming the console). In any case, I believe the main reason for this change is so that debug FSP builds can fit in flash. -- To view, visit https://review.coreboot.org/c/coreboot/+/81634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Gerrit-Change-Number: 81634 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:25:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
by Angel Pons (Code Review) 11 Apr '24

11 Apr '24

Attention is currently required from: Fabian Groffen, Felix Singer, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77046?usp=email ) Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H ...................................................................... Patch Set 7: Code-Review+1 (12 comments) File src/mainboard/gigabyte/ga-h77m-d3h/Kconfig: https://review.coreboot.org/c/coreboot/+/77046/comment/ae20006b_7adec9ed : PS7, Line 21: default 25 As per schematics, this board doesn't seem to use a DRAM reset gate GPIO at all (the DRAMRST# signal is wired directly between the CPU and the DIMM slots). But turns out that GPIO25 is mobile-only, so nothing should happen if coreboot tries to change its state. Which is good, because toggling a random GPIO that is wired elsewhere would be worse. TL;DR would be nice to add a comment: > Use GPIO25 because it does not exist on desktop PCHs and > because this board does not use a DRAM reset gate GPIO. File src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl: https://review.coreboot.org/c/coreboot/+/77046/comment/8f849b45_1581f0be : PS7, Line 7: Name (_ADR, 0x001E0000) This can't be correct because the board uses a dedicated PCIe-to-PCI bridge chip instead of the southbridge's conventional PCI port (which IIRC is only available on "corporate" PCH SKUs, e.g. Q-series) File src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl: PS7: Has this been tested? File src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb: https://review.coreboot.org/c/coreboot/+/77046/comment/de1ce0fc_ed2e5f3e : PS7, Line 5: subsystemid 0x1458 0x5000 Same ID already gets inherited, you can omit this line https://review.coreboot.org/c/coreboot/+/77046/comment/393efae2_e1fe2439 : PS7, Line 26: device ref mei2 off end # Management Engine Interface 2 I think the chipset devicetree already provides default on/off states for named devices, so you should omit entries for disabled devices (as long as they're disabled in the chipset devicetree). https://review.coreboot.org/c/coreboot/+/77046/comment/48137fd5_b05f9a13 : PS7, Line 36: device ref pcie_rp1 on end # PCIe Port #1 : device ref pcie_rp2 off end # PCIe Port #2 : device ref pcie_rp3 off end # PCIe Port #3 : device ref pcie_rp4 off end # PCIe Port #4 : device ref pcie_rp5 on # PCIe Port #5 : device pci 00.0 on # AR8161 GbE : end : end : device ref pcie_rp6 off end # PCIe Port #6 : device ref pcie_rp7 off end # PCIe Port #7 : device ref pcie_rp8 off end # PCIe Port #8 Based on what I can see in board pictures [1], this is not accurate. There should be at least *four* root ports enabled: - second PCIe x16 slot (electrical) - onboard Ethernet (AR8161 GbE) - PCIe x1 slot - ITE PCIe-to-PCI bridge (likely same chip as in `mb/gigabyte/ga-h61m-series`) According to the schematics for the GA-Z77M-D3H (which is likely identical, save for minor differences between board revisions), looks like the correct mapping should be: ``` device ref pcie_rp1 on end # RP #1: PCIEX4 slot device ref pcie_rp2 off end # RP #2 device ref pcie_rp3 off end # RP #3 device ref pcie_rp4 off end # RP #4 device ref pcie_rp5 on # RP #5: AR8161 GbE device pci 00.0 on end end device ref pcie_rp6 on end # RP #6: PCIEX1 slot device ref pcie_rp7 on end # RP #7: IT8892E PCIe-to-PCI device ref pcie_rp8 off end # RP #8 ``` [1]: https://imgur.com/a/sq6MNFd https://review.coreboot.org/c/coreboot/+/77046/comment/5115f435_a7d935fa : PS7, Line 50: device ref pci_bridge on end # PCI bridge The PCI bridge in the southbridge doesn't seem to be used. You should disable it. https://review.coreboot.org/c/coreboot/+/77046/comment/d32e0017_90600dce : PS7, Line 107: device pci 1f.4 off end I don't think this device is supposed to exist File src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl: https://review.coreboot.org/c/coreboot/+/77046/comment/3b137883_a3f40dfa : PS7, Line 10: // OEM revision I think autoport hardcodes this value, as well as the comment. I'd drop the comment, since it's not true. File src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/77046/comment/3a833b81_50cd860b : PS7, Line 12: HDMI1 DVI-D connector https://review.coreboot.org/c/coreboot/+/77046/comment/c50effd0_578b0910 : PS7, Line 13: HDMI3 HDMI connector https://review.coreboot.org/c/coreboot/+/77046/comment/1fbaaf74_b3782df0 : PS7, Line 14: Analog VGA connector -- To view, visit https://review.coreboot.org/c/coreboot/+/77046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab Gerrit-Change-Number: 77046 Gerrit-PatchSet: 7 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Thu, 11 Apr 2024 11:23:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tree: Drop unused <string.h>
by Elyes Haouas (Code Review) 11 Apr '24

11 Apr '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81818?usp=email ) Change subject: tree: Drop unused <string.h> ...................................................................... tree: Drop unused <string.h> Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81818 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/storage/pci_sdhci.c M src/drivers/amd/agesa/s3_mtrr.c M src/drivers/efi/option.c M src/drivers/ipmi/ocp/ipmi_sel.c M src/drivers/sof/sof.c M src/mainboard/google/geralt/panel.c M src/mainboard/lenovo/x1_carbon_gen1/early_init.c M src/mainboard/starlabs/lite/variants/glk/gpio.c M src/mainboard/starlabs/lite/variants/glkr/gpio.c M src/mainboard/starlabs/starbook/variants/cml/romstage.c M src/northbridge/intel/gm45/iommu.c M src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c M src/soc/amd/mendocino/fsp_misc_data_hob.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/mediatek/mt8195/pcie.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3399/clock.c 20 files changed, 0 insertions(+), 20 deletions(-) Approvals: Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index de9dd1b..f7922d4 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -4,7 +4,6 @@ #include <device/pci.h> #include <device/pci_ops.h> #include <stdint.h> -#include <string.h> #include "sd_mmc.h" #include "storage.h" diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index 51e8a4d..b085b4d 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -6,7 +6,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> -#include <string.h> #include <northbridge/amd/agesa/agesa_helper.h> /* TODO: Do we want MTRR_DEF_TYPE_MSR too? */ diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c index 3960cfc..8e5b326 100644 --- a/src/drivers/efi/option.c +++ b/src/drivers/efi/option.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdlib.h> -#include <string.h> #include <option.h> #include <smmstore.h> diff --git a/src/drivers/ipmi/ocp/ipmi_sel.c b/src/drivers/ipmi/ocp/ipmi_sel.c index f7605ec..157bdbd 100644 --- a/src/drivers/ipmi/ocp/ipmi_sel.c +++ b/src/drivers/ipmi/ocp/ipmi_sel.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <drivers/ipmi/ipmi_if.h> -#include <string.h> #include "ipmi_ocp.h" diff --git a/src/drivers/sof/sof.c b/src/drivers/sof/sof.c index db945aa..8cd577e 100644 --- a/src/drivers/sof/sof.c +++ b/src/drivers/sof/sof.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/path.h> -#include <string.h> #include "chip.h" diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index 3f55cac..9bf7416 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -11,7 +11,6 @@ #include <soc/i2c.h> #include <soc/pmif.h> #include <soc/regulator.h> -#include <string.h> #include "gpio.h" #include "panel.h" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index 00d94e6..b525a0b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <string.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/starlabs/lite/variants/glk/gpio.c b/src/mainboard/starlabs/lite/variants/glk/gpio.c index f24ed9e..321082c 100644 --- a/src/mainboard/starlabs/lite/variants/glk/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glk/gpio.c @@ -3,7 +3,6 @@ #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include <string.h> #include <variants.h> #include <types.h> diff --git a/src/mainboard/starlabs/lite/variants/glkr/gpio.c b/src/mainboard/starlabs/lite/variants/glkr/gpio.c index 11a7d31..41d2b47 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/gpio.c +++ b/src/mainboard/starlabs/lite/variants/glkr/gpio.c @@ -3,7 +3,6 @@ #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> -#include <string.h> #include <variants.h> #include <types.h> diff --git a/src/mainboard/starlabs/starbook/variants/cml/romstage.c b/src/mainboard/starlabs/starbook/variants/cml/romstage.c index 75a19e5..372f8b0 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/cml/romstage.c @@ -5,7 +5,6 @@ #include <option.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> -#include <string.h> #include <types.h> static unsigned int get_memory_config_straps(void) diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 4f6e000..6a68dff 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <string.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c b/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c index 6e615dd..aaf492e 100644 --- a/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c +++ b/src/soc/amd/common/fsp/fsp_ccx_cppc_hob.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <FspGuids.h> #include <fsp/util.h> -#include <string.h> #include <types.h> diff --git a/src/soc/amd/mendocino/fsp_misc_data_hob.c b/src/soc/amd/mendocino/fsp_misc_data_hob.c index ed35800..e5eae02 100644 --- a/src/soc/amd/mendocino/fsp_misc_data_hob.c +++ b/src/soc/amd/mendocino/fsp_misc_data_hob.c @@ -5,7 +5,6 @@ #include <fsp/amd_misc_data.h> #include <fsp/amd_misc_data_hob.h> #include <fsp/util.h> -#include <string.h> #include <types.h> static enum cb_err get_amd_misc_data_hob(const struct amd_misc_data **fsp_misc_data, int min_revision) diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index ca4e5e1..c8d1978 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -20,7 +20,6 @@ #include <soc/pm.h> #include <soc/soc_chip.h> #include <soc/systemagent.h> -#include <string.h> #include <types.h> /* diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 6ed018c..83418dc 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -11,7 +11,6 @@ #include <soc/soc_util.h> #include <soc/util.h> #include <stdlib.h> -#include <string.h> #include <pc80/mc146818rtc.h> const EWL_PRIVATE_DATA *get_ewl_hob(void) diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index 7f60d68..960d0bb 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -8,7 +8,6 @@ #include <soc/pcie.h> #include <soc/pcie_common.h> #include <stdlib.h> -#include <string.h> #define PCIE_REG_BASE_PORT0 0x112f0000 #define PCIE_RST_CTRL_REG (PCIE_REG_BASE_PORT0 + 0x148) diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index a2dda39..9d330a6 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -5,7 +5,6 @@ #include <edid.h> #include <timer.h> #include <types.h> -#include <string.h> #include <soc/display/edp_aux.h> #include <soc/display/edp_reg.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index 5074317..5b36c4b 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -6,7 +6,6 @@ #include <soc/clock.h> #include <soc/display/edp_reg.h> #include <soc/display/edp_phy.h> -#include <string.h> #include <timer.h> static void edp_phy_ssc_en(bool en) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index c3a9ac2..b6960aa 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -12,7 +12,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <string.h> struct pll_div { u32 nr; diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 115d289..0b027ed 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -11,7 +11,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <string.h> struct pll_div { u32 refdiv; -- To view, visit https://review.coreboot.org/c/coreboot/+/81818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e216cbc4acf9571c65c345a1764e74485f89438 Gerrit-Change-Number: 81818 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) 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