Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81923?usp=email )
Change subject: mb/asus/p8z77-m[_pro]: Blink power LED during suspend
......................................................................
mb/asus/p8z77-m[_pro]: Blink power LED during suspend
Set GPIO27 of PCH to blink before going to sleep. This blinks the
power LED. Revert after waking up.
Tested on p8z77-m. Power LED blinks in suspend.
Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81923
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/asus/p8x7x-series/acpi/platform.asl
1 file changed, 10 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/asus/p8x7x-series/acpi/platform.asl b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
index 7da03bf..b16ced5 100644
--- a/src/mainboard/asus/p8x7x-series/acpi/platform.asl
+++ b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
@@ -2,9 +2,19 @@
Method(_PTS, 1)
{
+#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
+ /* blink power LED if not turning off */
+ If (Arg0 != 0x05)
+ {
+ GB27 = 1
+ }
+#endif
}
Method(_WAK, 1)
{
+#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
+ GB27 = 0
+#endif
Return(Package(){0, 0})
}
--
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Gerrit-Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Gerrit-Change-Number: 81923
Gerrit-PatchSet: 2
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81955?usp=email )
Change subject: mb/google/nissa/var/glassway: Add SPD IDs for two new memory parts
......................................................................
mb/google/nissa/var/glassway: Add SPD IDs for two new memory parts
Support Memory for Hynix H58G66AK6BX070 and Samsung
K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
H58G66AK6BX070 4 (0100)
K3KL9L90CM-MGCT 5 (0101)
BUG=b:335341310
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954
Signed-off-by: Daniel_Peng <Daniel_Peng(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955
Reviewed-by: Kapil Porwal <kapilporwal(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-by: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
M src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
M src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
3 files changed, 8 insertions(+), 2 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
Daniel Peng: Looks good to me, but someone else must approve
Kapil Porwal: Looks good to me, approved
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
index b4d82e9..3104c19 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
+++ b/src/mainboard/google/brya/variants/glassway/memory/Makefile.mk
@@ -1,10 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build486926698/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
SPD_SOURCES =
SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = K3KL8L80CM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT
SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 2(0b0010) Parts = H58G56AK6BX069
SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 3(0b0011) Parts = H9JCNNNBK3MLYR-N6E
+SPD_SOURCES += spd/lp5/set-0/spd-6.hex # ID = 4(0b0100) Parts = H58G66AK6BX070
+SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 5(0b0101) Parts = K3KL9L90CM-MGCT
diff --git a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
index 866132d3..ca68f99 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/dram_id.generated.txt
@@ -1,10 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Generated by:
-# /tmp/go-build472300524/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+# /tmp/go-build486926698/b001/exe/part_id_gen ADL lp5 src/mainboard/google/brya/variants/glassway/memory/ src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
H58G56AK6BX069 2 (0010)
H9JCNNNBK3MLYR-N6E 3 (0011)
+H58G66AK6BX070 4 (0100)
+K3KL9L90CM-MGCT 5 (0101)
diff --git a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
index deeb000..f742b0b 100644
--- a/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
+++ b/src/mainboard/google/brya/variants/glassway/memory/mem_parts_used.txt
@@ -13,3 +13,5 @@
K3KL6L60GM-MGCT
H58G56AK6BX069
H9JCNNNBK3MLYR-N6E
+H58G66AK6BX070
+K3KL9L90CM-MGCT
--
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81887?usp=email )
Change subject: soc/amd/glinda: Add support for A0 and B0 steppings
......................................................................
Patch Set 4: Code-Review+2
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81960/comment/e79ab5ea_443aa1ca :
PS1, Line 15: transition.
> > When we implement the x64 architecture for libpayload, we design the ABI expectation according to long mode
>
> So your problem is between coreboot and your payload, not "between
> libpayload and depthcharge"? I guess we should discuss the new ABI first.
>
> What do you mean with LB exactly? I see you're referring to the payload?
LB = libpayload
DC = depthcharge
to build 64-bit DC, we need to first build 64-bit LB. Now if coreboot switch to 32-bit while entering into the LB although we are expecting to load LB in 64-bit mode, hence the calling convention is not aligned.
I won't say if this is problem between DC and LB rather the design of DC is such a way that both DC and LB should follow the same architecture.
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/000fcc4d_33b0e025 :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
> Would it be possible to make it an offset? Then we could have a 32-bit entry
> point followed by a 64-bit one, and a coreboot that knows the new ABI could skip
> the first and jump directly to the new entry point. This would allow the most
> compatibility between coreboot and payloads, as we could say the 64-bit entry
> point is optional on both ends (except for X86S, ofc.).
>
> I guess the complexity of such a 32-bit entry point, that switches to long mode,
> would depend a lot on the expectations on page tables in the new ABI.
I'm following the guideline shared by Arthur in previous comment where we will have add new cmd line for cbfstool option `--64` for adding a 64-bit payload. based on this cmdline, cbfstool will inject additional tag to understand if this payload is 64bit or 32bit. later coreboot can search the header before jumping into correct ABI.
for chromeos builder, the chromeos_bootimage will inject payload/depthcharge into cbfs with `--64` cmdline for applicable platform.
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81960/comment/0d4afb4f_71750d00 :
PS1, Line 15: transition.
> When we implement the x64 architecture for libpayload, we design the ABI expectation according to long mode
So your problem is between coreboot and your payload, not "between
libpayload and depthcharge"? I guess we should discuss the new ABI first.
What do you mean with LB exactly? I see you're referring to the payload?
Patchset:
PS1:
I've no experience with such an ABI that involves page tables.
Looking at Linux [1], it seems they expect only the minimum,
kernel and all information passed should be identity mapped.
Should we follow this model? or should we make more guarantees
about the mapping?
Does anyone know what UPL wants to do?
[1] https://docs.kernel.org/arch/x86/boot.html?#id1
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/8015c05f_7e5572ad :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
> > > > > > AIUI, the payload handover and the coreboot tables are the most important […]
Would it be possible to make it an offset? Then we could have a 32-bit entry
point followed by a 64-bit one, and a coreboot that knows the new ABI could skip
the first and jump directly to the new entry point. This would allow the most
compatibility between coreboot and payloads, as we could say the 64-bit entry
point is optional on both ends (except for X86S, ofc.).
I guess the complexity of such a 32-bit entry point, that switches to long mode,
would depend a lot on the expectations on page tables in the new ABI.
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Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21:
Add some backgrounds for the reason to adopt dynamic _OSC generations. The code that is generated is as below. We can get that it includes the host bridge device name (\_SB.PM08) and locality (_PXM) ... (will be more cases and not limited to these).
In a static ASL, such info will be hard coded to fit for one SoC SKU, however, for different SoC/SKUs, we need multiple set of static ASLs.
For Xeon-SP codes starting from SPR, we need one set of SoC codes to support multiple SKUs (SPR -> SPR-XCC, SPR-MCC) or multiple SoC/SKUs (GNR -> GNR-SP, GNR-AP, SRF-SP, SRF-AP). Hence the dynamic code generations are more suitable.
Scope (\_SB.PM08)
{
Name (_PXM, Zero) // _PXM: Device Proximity
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
Return (\_SB.AR12) /* External reference */
}
Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
{
If ((Arg1 != One))
{
RETE = 0x08
Return (Arg3)
}
Local7 = Arg3
CreateDWordField (Local7, Zero, QSUP)
CreateDWordField (Arg3, Zero, RETE)
RETE = Zero
Local6 = Zero
If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
{
If ((Arg2 < 0x02))
{
RETE = 0x02
Return (Arg3)
}
CreateDWordField (Arg3, 0x04, SUPP)
CreateDWordField (Arg3, 0x08, CTRL)
CreateDWordField (Local7, 0x08, OTRL)
ToInteger (CTRL, Local0)
Local1 = 0x15
Local0 &= Local1
CTRL = Local0
If ((CTRL != OTRL))
{
RETE = 0x10
}
Local6 = One
}
If ((Local6 == Zero))
{
RETE = 0x04
}
Return (Arg3)
}
}
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