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Dinesh Gehlot has uploaded a new patch set (#47) to the change originally created by Tarun Tuli. ( https://review.coreboot.org/c/libgfxinit/+/69341?usp=email )
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Code-Review+1 by Dinesh Gehlot
Change subject: gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
......................................................................
gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
Pcode mailbox `CDCLK_PREPARE_FOR_CHANGE' command is not available till
BIOS Reset CPL and may fail when called too early.
This command is actually not mandatory to set the CDCLK sucessfully on
ADL platform. This patch keeps the `CDCLK_PREPARE_FOR_CHANGE' command
but ignores return errors if any.
Change-Id: I0514e404a7b580d1e35af7b39c1bd77183f11058
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
---
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
1 file changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/41/69341/47
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Dinesh Gehlot has uploaded a new patch set (#38) to the change originally created by Tim Wawrzynczak. ( https://review.coreboot.org/c/libgfxinit/+/67499?usp=email )
The following approvals got outdated and were removed:
Code-Review+1 by Angel Pons
Change subject: gma tgl: Add connector programming
......................................................................
gma tgl: Add connector programming
This patch adds support for enabling displays on both combo PHY ports
and Type-C ports over DP-Alt mode.
Verified eDP, HDMI (not Type-C), and DP Alt mode on google/delbin.
Change-Id: I908e8bef8451d21eecde9ce6defddc2b3df7f738
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
---
M common/hw-gfx-gma-config.ads.template
M common/hw-gfx-gma.adb
M common/hw-gfx-gma.ads
M common/tigerlake/Makefile.inc
A common/tigerlake/hw-gfx-gma-connectors-combo_phy.adb
A common/tigerlake/hw-gfx-gma-connectors-combo_phy.ads
A common/tigerlake/hw-gfx-gma-connectors-tc.adb
A common/tigerlake/hw-gfx-gma-connectors-tc.ads
M common/tigerlake/hw-gfx-gma-connectors.adb
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
10 files changed, 1,625 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/99/67499/38
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Change subject: Documentation: Update information about intelp2m
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
Patchset:
PS8:
I've found these changes useful when getting round to adding MTL support, so it's a +1 from me
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 1:
(1 comment)
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/bb8cb978_c5e731ab :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
> > Would it be possible to make it an offset? Then we could have a 32-bit entry
> > point followed by a 64-bit one, and a coreboot that knows the new ABI could skip
> > the first and jump directly to the new entry point. This would allow the most
> > compatibility between coreboot and payloads, as we could say the 64-bit entry
> > point is optional on both ends (except for X86S, ofc.).
> >
> > I guess the complexity of such a 32-bit entry point, that switches to long mode,
> > would depend a lot on the expectations on page tables in the new ABI.
>
I guess a minimal expectation of at least 4G identity mapped is reasonable. Iirc UPL does that too. I like the idea of multiple entry points over a CBFS attribute as it's indeed the best way to be remain compatible. Linux already has exactly this btw. Question remains on how to achieve this? Have an expectation on the namespace in the ELF file which cbfstool can pick up? .text._entry64?
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Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21:
> What differences are there that you would hard-code and that can't be put into […]
The server ASL example is quite long, I sent a mail to you (with an ASL example there) and let us discuss in mail?
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Hello Krystian Hebel, Michał Kopeć, Michał Żygowski, Piotr Król, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81963?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/protectli/vault_cml: use combo v1/v2 FSP
......................................................................
mb/protectli/vault_cml: use combo v1/v2 FSP
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/protectli/vault_cml/Kconfig
M src/mainboard/protectli/vault_cml/Kconfig.name
2 files changed, 5 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81963/2
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/f98211b3_15edc8ad :
PS1, Line 306: } else {
> Maybe to have soc_add_dram_resources(), soc_add_cxl_mem_resources() and soc_add_misc_resources()? Si […]
It's hard to review this change without knowing what the implementation of `soc_add_dram_resources` looks like for `chip_gen6.c`.
It currently looks like this (just a "TODO: not implemented yet" comment): https://review.coreboot.org/c/coreboot/+/81316/47/src/soc/intel/xeon_sp/chi…
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/d1b9d814_21587c8f :
PS1, Line 234: * @param mc_values List of system memory map variables.
> > As of now only TOHM_REG is used, but theoretically all 64bit defined maps might be related […]
Personally, I think to have the soc memory map codes to get a full picture of system memory map settings, a.k.a. the full list, would be helpful for potential usages, given its original design intention.
(P.S. I copy the full memory map list to show that, like TOHM_REG defined as a 64bit map item, there are other 64bit map items which might impact >4G maps in future as well.)
As a code movement patch, my personal preference is to keep the full list first. I can have a another patch to change the parameter to TOHM item only (but in future, we might need to add other items as parameters based on needs). Your opinion?
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/2445e74a_beb5f3d8 :
PS1, Line 306: } else {
> You could still split it further. Now you have an `if (CXL)` in `chip_gen1.c`. This […]
Maybe to have soc_add_dram_resources(), soc_add_cxl_mem_resources() and soc_add_misc_resources()? Since this is a code movement patch, I could have a separate patch for the further splits.
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