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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 1:
(3 comments)
File src/soc/intel/xeon_sp/chip_gen1.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/92d4f936_53fed3bd :
PS1, Line 234: * @param mc_values List of system memory map variables.
> Why pass the whole array? This makes the API more complicated than necessary. […]
As of now only TOHM_REG is used, but theoretically all 64bit defined maps might be related, hence I think it still makes sense to pass the full list. Another point worth mentioning is that the SoC maps are not limited to >4G maps (though most of case current being handled are for >4G maps), hence to have the knowledge of the full map will help. I updated the commit message to reflect this. Your opinion?
static struct map_entry memory_map[NUM_MAP_ENTRIES] = {
[TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"),
[MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"),
[MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"),
[MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"),
[TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"),
#if CONFIG(SOC_INTEL_HAS_NCMEM)
[NCMEM_BASE_REG] = MAP_ENTRY_BASE_64(VTD_NCMEM_BASE_CSR, "NCMEM_BASE"),
[NCMEM_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_NCMEM_LIMIT_CSR, 19, "NCMEM_LIMIT"),
#else
[ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"),
[ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"),
#endif
[TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"),
[TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"),
[VTDBAR_REG] = MAP_ENTRY_BASE_32(VTD_BAR_CSR, "VTD_BAR"),
};
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81958/comment/a2d2ba0f_25d81cd2 :
PS1, Line 306: } else {
> So there were already two different implementations. One without and one […]
Currently soc_mc_add_dram_resources holds all SoC specific mappings, CXL, >4G DRAM, and others (in future), hence the memory maps are simply split to common part and non-common part instead of a CXL part and non-CXL part. I updated the commit message to mention this.
https://review.coreboot.org/c/coreboot/+/81958/comment/c67ff5fe_2866c1ea :
PS1, Line 274: index +=
> Returning the count and adding it up is uncommon. And if reading the whole code, […]
Done
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
23 files changed, 1,185 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/47
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Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
soc/intel/xeon_sp: Add soc_add_dram_resources
SoC specific DRAM resource, e.g. 4GB above DRAM memory map, CXL,
et al, are different across SoC generations. This patch separates
the codes so that different SoC generations could have different
implementations.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie15b11e1f4cdc861324286b1397f9c5e431b74ab
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 82 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/81958/2
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Change subject: mb/asus/p8z77-m: Drop GPIO by I/O
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
would be good if you can try if CB:81926 fixed the underlying issue
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Change subject: mb/dell/optiplex_9020: Add support for TPM1.2 device
......................................................................
mb/dell/optiplex_9020: Add support for TPM1.2 device
These machines come with a TPM1.2 device by default. It is somewhat
obsolete these days, but there is no harm in enabling it.
Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/dell/optiplex_9020/Kconfig
M src/mainboard/dell/optiplex_9020/devicetree.cb
2 files changed, 5 insertions(+), 0 deletions(-)
Approvals:
Angel Pons: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
index 2de4a9a..38c3281 100644
--- a/src/mainboard/dell/optiplex_9020/Kconfig
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -12,7 +12,9 @@
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
+ select MEMORY_MAPPED_TPM
select NORTHBRIDGE_INTEL_HASWELL
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_LYNXPOINT
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
index dce5869..841285b 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -70,6 +70,9 @@
device pnp 2e.b off end # Floppy Controller
device pnp 2e.11 off end # Parallel Port
end
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
end
device pci 1f.2 on end # SATA controller 1
device pci 1f.3 on end # SMBus
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75144?usp=email )
Change subject: mb/asus/p8z77-m: Disable WDT1
......................................................................
mb/asus/p8z77-m: Disable WDT1
WDT1 is currently enabled but gives these errors:
[ERROR] ERROR: Resource didn't fit!!!
PNP: 002e.8 60 * size: 0x8 limit: fff io
[ERROR] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree
Therefore, just disable it, like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: Ie33c219eae60f55d272b261480283a02c2d502e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75144
Reviewed-by: Keith Hui <buurin(a)gmail.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
1 file changed, 1 insertion(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Keith Hui: Looks good to me, approved
Felix Held: Looks good to me, approved
diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
index 5d688fd..ee2fe9a 100644
--- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
+++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb
@@ -47,10 +47,7 @@
drq 0x22 = 0xd7 # Power down UART B and LPT
end
device pnp 2e.6 off end # CIR
- device pnp 2e.8 on # WDT1
- drq 0xe0 = 0x7f # GP07 output
- drq 0xe1 = 0x80 # GP07 high
- end
+ device pnp 2e.8 off end # WDT1
device pnp 2e.a on # ACPI
drq 0xe4 = 0x10 # Enable 3VSBSW#, needed for S3 suspend
drq 0xe7 = 0x11 # HWM reset by LRESET#, 0.5s S3 delay for compatibility
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Change subject: mb/asus/p8z77-m: Disable WDT1
......................................................................
Patch Set 5: Code-Review+2
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81926?usp=email )
Change subject: sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN
......................................................................
sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN
According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.
Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/superio/nuvoton/nct6779d/nct6779d.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h
index 85f4081..30694ea 100644
--- a/src/superio/nuvoton/nct6779d/nct6779d.h
+++ b/src/superio/nuvoton/nct6779d/nct6779d.h
@@ -22,7 +22,7 @@
/* virtual LDN for GPIO */
-#define NCT6779D_GPIOBASE ((0 << 8) | NCT6779D_WDT1_GPIO01_V)
+#define NCT6779D_GPIOBASE ((3 << 8) | NCT6779D_WDT1_GPIO01_V)
#define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT1_GPIO01_V)
#define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO12345678_V)
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Gerrit-Change-Number: 81926
Gerrit-PatchSet: 2
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-Reviewer: Eric Lai <ericllai(a)google.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81946?usp=email )
Change subject: nb/intel/gm45: Call `mb_post_raminit_setup()` later
......................................................................
nb/intel/gm45: Call `mb_post_raminit_setup()` later
The only implementations of `mb_post_raminit_setup()` in the tree are
found in Lenovo ThinkPads. These boards use this function to toggle a
SMBus mux, which makes the DIMM SPDs inaccessible. Given that the SPD
data is needed in `setup_sdram_meminfo()` and that there are no other
side-effects, simply move the call to `mb_post_raminit_setup()` after
the call to `setup_sdram_meminfo()`.
TEST=Verify SMBIOS Type 17 information for lenovo/x200 is correct.
Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81946
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/northbridge/intel/gm45/romstage.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Nico Huber: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 9ed3c00..bc17618 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -74,8 +74,6 @@
raminit(&sysinfo, s3resume);
- mb_post_raminit_setup();
-
/* Disable D4F0 (unknown signal controller). */
pci_and_config32(MCH_DEV, D0F0_DEVEN, ~0x4000);
@@ -93,6 +91,8 @@
setup_sdram_meminfo(&sysinfo);
+ mb_post_raminit_setup();
+
romstage_handoff_init(cbmem_initted && s3resume);
printk(BIOS_SPEW, "exit main()\n");
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I46abffa48e7e0848f9346ce9c6498860e4ece2da
Gerrit-Change-Number: 81946
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jean Lucas
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged