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Change subject: ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
......................................................................
ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
Generated using update_ec_headers.sh [EC-DIR].
The original include/ec_commands.h version in the EC repo is:
b3b35d6433 PPM: Rename ucsi_disabled to ucsi_enabled
The original include/ec_cmd_api.h version in the EC repo is:
562316a71e include: Add fingerprint host commands to ec_cmd_api.h
BUG=b:333078787
TEST=cros build-packages --board brox \
chromeos-bootimage depthcharge coreboot
TEST=cros build-packages --board brya \
chromeos-bootimage depthcharge coreboot
BRANCH=none
Change-Id: I94b509cd6ad8f24bfc3b44ef02633d06320f1e22
Signed-off-by: Pavan Holla <pholla(a)google.com>
---
M src/ec/google/chromeec/ec_commands.h
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/81965/3
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81960?usp=email )
Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 2:
(1 comment)
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/2eec302d_419cb3fe :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
> > > > > > > Would it be possible to make it an offset? Then we could have a 32-bit entry
> > > > > > > point followed by a 64-bit one, and a coreboot that knows the new ABI could skip
> > > > > > > the first and jump directly to the new entry point. This would allow the most
> > > > > > > compatibility between coreboot and payloads, as we could say the 64-bit entry
> > > > > > > point is optional on both ends (except for X86S, ofc.).
> > > > > > >
> > > > > > > I guess the complexity of such a 32-bit entry point, that switches to long mode,
> > > > > > > would depend a lot on the expectations on page tables in the new ABI.
> > > > > >
> > > > >
> > > > > I guess a minimal expectation of at least 4G identity mapped is reasonable. Iirc UPL does that too. I like the idea of multiple entry points over a CBFS attribute as it's indeed the best way to be remain compatible. Linux already has exactly this btw. Question remains on how to achieve this? Have an expectation on the namespace in the ELF file which cbfstool can pick up? .text._entry64?
> > > >
> > > > can we review CB:81964 that adds the payload cbfs attribute for 64-bit. Then this CL has now updated to fetch the cbfs attribute rather reading any static Kconfig.
> > >
> > > following kernel concurrent 32-bit and 64-bit entry implementation may not be desired in AP FW as out configuration are very much static. We have to anyway select Kconfig in SoC to know if we are building 32-bit coreboot vs 64-bit coreboot hence, rather than complicating the flow, not sure what else we will bring by adding kernel like implementation while transferring control from coreboot to payload.
> > >
> >
> > My previous comment explained that building coreboot and payload together is not the only way of doing things and should not be assumed... Entering 64bit mode from in the payload itself with a 32bit entry point can be done in 12 instructions. That's not too complicated and should be considered with the dual entry point strategy.
> >
> > > Anyway, lets review this CL to ensure we have atleast some ways to launch 64-bit payload from a 64-bit coreboot w/o lowering into 32-bit mode. Later we can desire more scalable approach for handoff. btw, i will bring x64 support cls next for libpayload.
> >
> > Let's not rush this. An ABI needs to be well designed and well documented. I don't think the fix/improve later approach is good here, as it implies breaking the ABI that worked at some point. If you want a 64bit libpayload, maybe start with a 32bit entry point that jumps to 64bit, which should work as is. In the meanwhile let's have a discussion on the ML on what the ABI would look like?
>
> I respectfully disagree with your approach.
>
> The problem statement is straightforward:
>
> coreboot currently always enters payload/libpayload in 32-bit mode, even when Coreboot is built natively for 64-bit mode. As explained, we need to ensure that we have support for 64-bit direct entry without trunking.
>
Why do you need that without trunking? Are you talking about HW that does not have 32bit support or do you want to load/jump to the payload above 4G?
> I agree with you that we should add things to the payload CBFS to make things dynamic so that Coreboot can decide to jump either directly into 64-bit mode or fall back to 32-bit.
>
> I am not sure what is being broken by this approach. We are enabling 64-bit mode for payload and testing it seamlessly in parallel to 32-bit entry.
>
If we decide on a multiple entry point approach, then you end up with 2 ways: one with multiple entry points and one with an attribute indicating in which mode the payload works. That's 2 ways to do the same and since ABI needs to be stable that's not a good situation.
> If you wish to improve how the entry point should be handled in the future, that can be done separately. I am not sure why I need to hold off my activity or do things by your means.
>
Improving probably means breaking an ABI compatibility in the future. That's not a good idea.
> As I stated earlier, I will provide the libpayload 64-bit support code so you can examine how the entry point would appear. I ask that you do not combine this effort with unified payload. Unified payload is still in the planning stages, but enabling 64-bit support in coreboot/payload has business value; thus, the priority should not be the same at your end as it is at mine.
The unified payload stuff indeed should not trump your business needs and I'm not suggesting to wait for that to happen. However I do think that thoughtful design and discussion needs to happen around the introduction of a ABI, before moving forward. In my opinion that should be a priority before merging something that works.
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Change subject: Hide typec ACPI device if UCSI is supported
......................................................................
Patch Set 2:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81967/comment/892ee6c1_5ae8aab6 :
PS2, Line 7: Hide typec ACPI device if UCSI is supported
Nit:
`ec/google/chromeec: Do not fill TypeC ACPI device when UCSI is enabled.`
https://review.coreboot.org/c/coreboot/+/81967/comment/b8062de4_7f8a545b :
PS2, Line 9: remove
We are not removing. Rather we are not filling the TypeC ACPI device when UCSI is enabled. So I will rephrase the commit message accordingly.
https://review.coreboot.org/c/coreboot/+/81967/comment/e8f4b90a_10361f0a :
PS2, Line 17: b/333074788 and https://crrev.com/c/5421069 track the corresponding EC
: change to add CBI.
: https://crrev.com/c/5416841 is the change for adding the feature flag
These links probably are access controlled and hence the community may not have access to it. You can remove them.
https://review.coreboot.org/c/coreboot/+/81967/comment/d612e29a_7eb233d0 :
PS2, Line 23:
Cq-Depend: chromium:5416841
File src/ec/google/chromeec/ec_acpi.c:
https://review.coreboot.org/c/coreboot/+/81967/comment/147f2faa_452eb01a :
PS2, Line 161: /* UCSI implementations do not require an ACPI device
: * with mux info since the linux kernel doesn't set
: * the muxes. */
Nit: Coreboot allows 96 chars per line. Also here is the guideline regarding multi-line comments - https://doc.coreboot.org/contributing/coding_style.html#commenting
Specifically this can be updated as:
```
/* UCSI implementations do not require an ACPI device with mux info since the
linux kernel doesn't set the muxes. */
```
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Hello Krystian Hebel, Michał Kopeć, Michał Żygowski, Piotr Król, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/protectli/vault_cml: use combo v1/v2 FSP
......................................................................
mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
R configs/config.protectli_cml_vp46xx
D configs/config.protectli_vp4630_vp4650
M src/mainboard/protectli/vault_cml/Kconfig
M src/mainboard/protectli/vault_cml/Kconfig.name
4 files changed, 6 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81963/7
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Change subject: mb/protectli/vault_cml: use combo v1/v2 FSP
......................................................................
mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch config to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
R configs/config.protectli_cml_vp46xx
D configs/config.protectli_vp4630_vp4650
A configs/config.protectli_vp46xx_txt
M src/mainboard/protectli/vault_cml/Kconfig
M src/mainboard/protectli/vault_cml/Kconfig.name
5 files changed, 24 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81963/6
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Change subject: mb/protectli/vault_cml: use combo v1/v2 FSP
......................................................................
mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
R configs/config.protectli_cml_vp46xx
D configs/config.protectli_vp4630_vp4650
A configs/config.protectli_vp46xx_txt
M src/mainboard/protectli/vault_cml/Kconfig
M src/mainboard/protectli/vault_cml/Kconfig.name
5 files changed, 24 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81963/5
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Change subject: configs/config.protectli_vault_cml*: update for combo v1/v2 FSP
......................................................................
Abandoned
Squashed into https://review.coreboot.org/c/coreboot/+/81963
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I'd like you to reexamine a change. Please visit
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Change subject: mb/protectli/vault_cml: use combo v1/v2 FSP
......................................................................
mb/protectli/vault_cml: use combo v1/v2 FSP
Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
A configs/config.protectli_cml_vp46xx
D configs/config.protectli_vp4630_vp4650
D configs/config.protectli_vp4670
A configs/config.protectli_vp46xx_txt
M src/mainboard/protectli/vault_cml/Kconfig
M src/mainboard/protectli/vault_cml/Kconfig.name
6 files changed, 88 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/81963/4
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