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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#10).
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Verified+1 by build bot (Jenkins)
Change subject: [for test] upgrade crossgcc
......................................................................
[for test] upgrade crossgcc
Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
R util/crossgcc/patches/acpica-unix-20240321_iasl.patch
R util/crossgcc/patches/gcc-14-20240414_asan_shadow_offset_callback.patch
R util/crossgcc/patches/gcc-14-20240414_gnat.patch
R util/crossgcc/patches/gcc-14-20240414_libcpp.patch
R util/crossgcc/patches/gcc-14-20240414_libgcc.patch
R util/crossgcc/patches/gcc-14-20240414_musl_poisoned_calloc.patch
R util/crossgcc/patches/gcc-14-20240414_rv32iafc.patch
D util/crossgcc/patches/nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
D util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum
A util/crossgcc/sum/acpica-unix-20240321.tar.gz.cksum
D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/clang-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/cmake-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum
A util/crossgcc/sum/cmake-3.29.2.tar.gz.cksum
D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum
A util/crossgcc/sum/gcc-14-20240414.tar.xz.cksum
D util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/libunwind-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/lld-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum
A util/crossgcc/sum/llvm-18.1.4.src.tar.xz.cksum
D util/crossgcc/sum/nasm-2.16.01.tar.bz2.cksum
A util/crossgcc/sum/nasm-2.16.03.tar.bz2.cksum
31 files changed, 54 insertions(+), 286 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/10
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Change subject: arch/x86: Enable long mode entry into payload for x86_64 support
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81960/comment/cec64804_35640213 :
PS1, Line 15: transition.
> Why would there be such issues? wouldn't libpayload be responsible
> to switch to long mode properly? The payload (depthcharge) should be
> only C code, isn't it?
Please take a look into https://github.com/coreboot/coreboot/blob/main/payloads/libpayload/arch/x86… In this case, the expectation is static, like libpayload enters into protected mode. Therefore, all the information expected from coreboot are based on 32-bit calling convention.
When we implement the x64 architecture for libpayload, we design the ABI expectation according to long mode and also build the libpayload using a 64-bit compiler (I will submit those CLs next). However, if coreboot always switches back to protected mode, then the expectation at the x64/head.S file will not match compared to the 32-bit libpayload entry.
for example: to fetch the coreboot table in 32-bit mode
```
/* save pointer to coreboot tables */
movl 4(%esp), %eax
movl %eax, cb_header_ptr
```
ideally a 64-bit lb code would expect the same data from RSI
```
movq %rsi, cb_header_ptr
```
Now that we are in 64-bit LB and expect to see the proper data in RSI, we noticed that the calling convention is not aligned between coreboot and libpayload.
Therefore, we opted for this option, where we decide at compile time how we would like to pass this information to libpayload. Since building libpayload in 64-bit is a static information, a platform that decides to build LB in 64-bit can also select this Kconfig to ensure there is no intermediate switch between 64-bit and 32-bit.
File src/arch/x86/boot.c:
https://review.coreboot.org/c/coreboot/+/81960/comment/0b82af5d_90de517c :
PS1, Line 25: if (CONFIG(PAYLOAD_X86_64_SUPPORT)) {
> AIUI, the payload handover and the coreboot tables are the most important
> ABI pieces of coreboot. Making this a compile-time option would mean that
> the resulting coreboot is suddenly incompatible to all prior (x86) payload
> builds. So, shouldn't this be decided at runtime, maybe based on information
> from CBFS?
Is it not a fact that using a 64-bit toolchain to compile the libpayload is also a static piece of information? If so, then why are we not allowing a configuration to also enter LB in the desired 64-bit mode instead of limiting it to 32-bit?
Currently, the default/non-configurable decision about LB entry is always in protected mode.
This CL allows for one more option where 64-bit direct entry is also possible, hence all of the following options are now valid:
1. 64-bit CB / 32-bit LB (using protected mode)
2. 64-bit CB / 64-bit LB (using long mode)
3. 32-bit CB / 32-bit LB
If we are relying on the runtime information about coreboot operational mode and using this information to decide whether to jump into LB, then wouldn't that limit #1 (where a protected mode entry into the libpayload is not possible while using 64-bit coreboot)? Perhaps not everyone wishes to use a 64-bit payload, so it would be better to keep those selections static based on the selection of payload mode.
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Change subject: mb/google/brox: Move hda verb to variant dir
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Suggest create the new API to return different array from variants.
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Change subject: mb/google/brox: Create lotso variant
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Patch Set 6: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
Patch Set 19: Code-Review+2
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Change subject: mb/google/brox/var/greenbayupoc: Add fw_config field for storage
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Hi all, […]
Acknowledged
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Change subject: mb/google/brox/var/greenbayupoc: Add fw_config field for storage
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Patch Set 3: Code-Review+2
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Change subject: util/ifdtool: Add support for checking GPR0 status
......................................................................
Patch Set 5:
(1 comment)
File util/ifdtool/ifdtool.c:
https://review.coreboot.org/c/coreboot/+/81928/comment/07cc8efa_56162b11 :
PS4, Line 1802: reg.data.write_protect_en
> Yes, that's what I meant. My point is that just because the enable bit is set, it doesn't necessarily mean protection is enabled. E.g. if the range is 0, it's not really enabled.
I'm agree with you. Since the purpose of `is_gpr0_protected()` is to know GPR0 protected is enabled/disabled, so check whole register should be safer.
I will try to do it in `is_gpr0_protected()`, will update once I complete.
> Can I ask what you're planning to use this for? Is it just for developers to use locally, or are you planning to use it in some automated process / test?
It's for developers to use.
Thank you.
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Change subject: mb/google/nissa/var/anraggar: Add cbj_sleeve to control mic jack
......................................................................
Patch Set 19:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81774/comment/3dda46ab_389b2c76 :
PS18, Line 7: Add cbj_sleeve to control mic jack
:
> Also mention that you replace the generic driver?
Done
https://review.coreboot.org/c/coreboot/+/81774/comment/b114bd62_1b6b2736 :
PS18, Line 9: Added
> Add
Done
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81774/comment/2cca3785_8f5609d9 :
PS18, Line 5: select DRIVERS_I2C_RT5645
> Please reorder.
Done
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